Travelled to:1 × France
1 × Germany
1 × Ireland
8 × USA
Collaborated with:W.Shi C.J.Alpert C.C.N.Sze S.Hu Y.Wei N.Viswanathan G.Nam N.Y.Zhou M.Waghmode J.Hu S.S.Sapatnekar M.Stagitis S.Carberry K.F.McCoy M.D.Moffitt D.A.Papa R.Kanj R.V.Joshi J.Hayes S.R.Nassif N.Y.Zhou T.Jindal C.B.Winn W.Liu Y.Li S.K.Karandikar L.N.Reddy A.D.Huber G.E.Téllez D.Keller
Talks about:buffer (6) time (5) insert (4) design (4) algorithm (3) optim (3) routabl (2) minimum (2) driven (2) closur (2)
Person: Zhuo Li
DBLP: Li:Zhuo
Contributed to:
2013
2013
201320122010200920082007200620052003Wrote 15 papers:
- DAC-2013-LiuWSALLV #constraints #design #estimation
- Routing congestion estimation with real design constraints (WHL, YW, CCNS, CJA, ZL, YLL, NV), p. 8.
- DATE-2013-WeiLSHAS #design #effectiveness #named
- CATALYST: planning layer directives for effective design closure (YW, ZL, CCNS, SH, CJA, SSS), pp. 1873–1878.
- SIGIR-2013-LiSCM #towards
- Towards retrieving relevant information graphics (ZL, MS, SC, KFM), pp. 789–792.
- DAC-2012-KanjJLHN #estimation #multi
- Yield estimation via multi-cones (RK, RVJ, ZL, JH, SRN), pp. 1107–1112.
- DAC-2012-LiANSVZ #design #physics #predict
- Guiding a physical design closure system to produce easier-to-route designs with more predictable timing (ZL, CJA, GJN, CCNS, NV, NYZ), pp. 465–470.
- DAC-2012-ViswanathanASLW #benchmark #contest #metric
- The DAC 2012 routability-driven placement contest and benchmark suite (NV, CJA, CCNS, ZL, YW), pp. 774–782.
- DAC-2012-WeiSVLARHTKS #evaluation #named
- GLARE: global and local wiring aware routability evaluation (YW, CCNS, NV, ZL, CJA, LNR, ADH, GET, DK, SSS), pp. 768–773.
- DAC-2010-JindalAHLNW #detection #logic
- Detecting tangled logic structures in VLSI netlists (TJ, CJA, JH, ZL, GJN, CBW), pp. 603–608.
- DAC-2009-HuLA #approximate #polynomial
- A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion (SH, ZL, CJA), pp. 424–429.
- DAC-2008-MoffittPLA #optimisation
- Path smoothing via discrete optimization (MDM, DAP, ZL, CJA), pp. 724–727.
- DAC-2007-ZhouLS #bound #embedded #hybrid #multi #performance #using
- Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method (NYZ, ZL, WS), pp. 835–840.
- DAC-2006-HuAHKLSS #algorithm #performance
- Fast algorithms for slew constrained minimum cost buffering (SH, CJA, JH, SKK, ZL, WS, CCNS), pp. 308–313.
- DAC-2006-WaghmodeLS #scalability
- Buffer insertion in large circuits with constructive solution search techniques (MW, ZL, WS), pp. 296–301.
- DATE-2005-LiS05a #algorithm
- An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types (ZL, WS), pp. 1324–1329.
- DAC-2003-ShiL #algorithm
- An O(nlogn) time algorithm for optimal buffer insertion (WS, ZL), pp. 580–585.