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Travelled to:
1 × Germany
17 × USA
5 × France
Collaborated with:
J.Hu C.H.Kim V.Nookala S.K.Karandikar N.Maheshwari V.Mishra B.Goplen J.Singh S.V.Kumar M.Zhao S.R.Nassif C.J.Alpert B.Boghrati Q.Liu H.Chang Y.Zhan R.B.Deokar P.Zhou T.Kolpe A.Zhai C.V.Kashyap J.Gu P.Saxena A.K.Sultania D.Sylvester H.Qian M.Ketkar K.Kasamsetty V.Sundararajan K.K.Parhi Y.Wei Z.Li C.C.N.Sze C.Li W.Luo B.D.Bel J.Kim J.Kung I.Han Y.Shin P.Yuh C.Yang Y.Chang Y.Chen D.J.Lilja Z.Luo H.Su P.Villarrubia J.Keane H.Eom T.T.Kim S.Hu R.Panda T.Edwards R.Chaudhry D.Blaauw E.Haritan K.Keutzer A.Devgan D.Kirkpatrick S.Meier D.Pryor T.Spyrou N.Viswanathan L.N.Reddy A.D.Huber G.E.Téllez D.Keller
Talks about:
power (7) optim (7) analysi (6) circuit (5) size (5) statist (4) delay (4) base (4) placement (3) algorithm (3)

Person: Sachin S. Sapatnekar

DBLP DBLP: Sapatnekar:Sachin_S=

Facilitated 1 volumes:

DAC 2010Ed

Contributed to:

DAC 20152015
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DAC 20112011
DATE 20112011
DAC 20082008
DAC 20072007
DAC 20062006
DAC 20052005
DAC 20042004
DATE v1 20042004
DATE v2 20042004
DAC 20032003
DAC 20022002
DAC 20012001
DAC 20002000
DAC 19991999
DATE 19981998
DAC 19971997
DAC 19951995
DAC 19941994

Wrote 39 papers:

DAC-2015-LiLSH #approximate #optimisation #precise #synthesis
Joint precision optimization and high level synthesis for approximate computing (CL, WL, SSS, JH), p. 6.
DATE-2014-BelKKS #fault #multi
Improving STT-MRAM density through multibit error correction (BDB, JK, CHK, SSS), pp. 1–6.
DAC-2013-MishraS #grid #power management
The impact of electromigration in copper interconnects on power grid integrity (VM, SSS), p. 6.
DATE-2013-WeiLSHAS #design #effectiveness #named
CATALYST: planning layer directives for effective design closure (YW, ZL, CCNS, SH, CJA, SSS), pp. 1873–1878.
DATE-2013-ZhouMS #locality #optimisation #power management
Placement optimization of power supply pads based on locality (PZ, VM, SSS), pp. 1655–1660.
DAC-2012-WeiSVLARHTKS #evaluation #named
GLARE: global and local wiring aware routability evaluation (YW, CCNS, NV, ZL, CJA, LNR, ADH, GET, DK, SSS), pp. 768–773.
DAC-2011-KungHSS #optimisation
Thermal signature: a simple yet accurate thermal index for floorplan optimization (JK, IH, SSS, YS), pp. 108–113.
DATE-2011-BoghratiS #analysis #grid #performance #power management #random
A scaled random walk solver for fast power grid analysis (BB, SSS), pp. 38–43.
DATE-2011-KolpeZS #clustering #manycore #power management
Enabling improved power management in multicore processors through clustered DVFS (TK, AZ, SSS), pp. 293–298.
DAC-2008-KumarKS #analysis #framework
A framework for block-based timing sensitivity analysis (SVK, CVK, SSS), pp. 688–693.
DAC-2008-SapatnekarHKDKMPS #manycore
Reinventing EDA with manycore processors (SSS, EH, KK, AD, DK, SM, DP, TS), pp. 126–127.
DAC-2008-YuhSYC #algorithm
A progressive-ILP based routing algorithm for cross-referencing biochips (PHY, SSS, CLY, YWC), pp. 284–289.
DAC-2007-GoplenS #3d
Placement of 3D ICs with Thermal and Interlayer Via Considerations (BG, SSS), pp. 626–631.
DAC-2007-GuSK #modelling #random #statistics
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift (JG, SSS, CHK), pp. 87–92.
DAC-2007-KumarKS #synthesis
NBTI-Aware Synthesis of Digital Circuits (SVK, CHK, SSS), pp. 370–375.
DAC-2007-LiuS #predict #process #scalability #statistics
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations (QL, SSS), pp. 497–502.
DAC-2006-KeaneEKSK #framework #logic
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing (JK, HE, TTHK, SSS, CHK), pp. 425–428.
DAC-2006-SinghS #analysis #component #correlation #independence #parametricity #statistics #using
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis (JS, SSS), pp. 155–160.
DAC-2005-ChangS #analysis #correlation #power management #process
Full-chip analysis of leakage power under process variations, including spatial correlations (HC, SSS), pp. 523–528.
Net weighting to reduce repeater counts during placement (BG, PS, SSS), pp. 503–508.
DAC-2005-NookalaCLS #approach #architecture #design #statistics #using
Microarchitecture-aware floorplanning using a statistical design of experiments approach (VN, YC, DJL, SSS), pp. 579–584.
DAC-2005-SinghNLS #geometry #programming #robust
Robust gate sizing by geometric programming (JS, VN, ZQL, SSS), pp. 315–320.
A method for correcting the functionality of a wire-pipelined circuit (VN, SSS), pp. 570–575.
DAC-2004-SultaniaSS #trade-off
Tradeoffs between date oxide leakage and delay for dual Tox circuits (AKS, DS, SSS), pp. 761–766.
DATE-v1-2004-ZhanS #optimisation #polynomial #programming #using
Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming (YZ, SSS), pp. 622–629.
DATE-v2-2004-KarandikarS #implementation #performance
Fast Comparisons of Circuit Implementations (SKK, SSS), pp. 910–915.
DAC-2003-QianNS #network #random
Random walks in a supply network (HQ, SRN, SSS), pp. 93–98.
DAC-2002-SuHSN #network
Congestion-driven codesign of power and signal networks (HS, JH, SSS, SRN), pp. 64–69.
DAC-2001-AlpertHSV #resource management
A Practical Methodology for Early Buffer and Wire Resource Allocation (CJA, JH, SSS, PV), pp. 189–194.
DAC-2001-KarandikarS #logic
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect (SKK, SSS), pp. 377–382.
DAC-2001-ZhaoS #algorithm #pattern matching
A New Structural Pattern Matching Algorithm for Technology Mapping (MZ, SSS), pp. 371–376.
DAC-2000-KetkarKS #modelling
Convex delay models for transistor sizing (MK, KK, SSS), pp. 655–660.
DAC-2000-SundararajanSP #named
MINFLOTRANSIT: min-cost flow based transistor sizing tool (VS, SSS, KKP), pp. 649–664.
DAC-2000-ZhaoPSECB #analysis #network
Hierarchical analysis of power distribution networks (MZ, RP, SSS, TE, RC, DB), pp. 150–155.
DAC-1999-HuS #named
FAR-DS: Full-Plane AWE Routing with Driver Sizing (JH, SSS), pp. 84–89.
DATE-1998-MaheshwariS #performance #scalability
Efficient Minarea Retiming of Large Level-Clocked Circuits (NM, SSS), pp. 840–845.
DAC-1997-MaheshwariS #algorithm
An Improved Algorithm for Minimum-Area Retiming (NM, SSS), pp. 2–7.
DAC-1995-DeokarS #fresh look #optimisation
A Fresh Look at Retiming Via Clock Skew Optimization (RBD, SSS), pp. 310–315.
DAC-1994-Sapatnekar #optimisation
RC Interconnect Optimization Under the Elmore Delay Model (SSS), pp. 387–391.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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