Travelled to:1 × France
1 × Germany
4 × USA
Collaborated with:C.J.Alpert Z.Li J.Hu Y.Wei N.Viswanathan W.Shi S.Hu S.S.Sapatnekar A.B.Kahng Q.Wang G.Venkataraman F.Liu G.Nam N.Y.Zhou W.Liu Y.Li S.K.Karandikar Y.Lu X.Hong Q.Zhou Y.Cai L.Huang L.N.Reddy A.D.Huber G.E.Téllez D.Keller
Talks about:design (4) placement (3) routabl (2) driven (2) closur (2) buffer (2) clock (2) time (2) rout (2) constraint (1)
Person: Cliff C. N. Sze
DBLP: Sze:Cliff_C=_N=
Contributed to:
2013
20132012200620062005Wrote 10 papers:
- DAC-2013-LiuWSALLV #constraints #design #estimation
- Routing congestion estimation with real design constraints (WHL, YW, CCNS, CJA, ZL, YLL, NV), p. 8.
- DATE-2013-WeiLSHAS #design #effectiveness #named
- CATALYST: planning layer directives for effective design closure (YW, ZL, CCNS, SH, CJA, SSS), pp. 1873–1878.
- DAC-2012-LiANSVZ #design #physics #predict
- Guiding a physical design closure system to produce easier-to-route designs with more predictable timing (ZL, CJA, GJN, CCNS, NV, NYZ), pp. 465–470.
- DAC-2012-ViswanathanASLW #benchmark #contest #metric
- The DAC 2012 routability-driven placement contest and benchmark suite (NV, CJA, CCNS, ZL, YW), pp. 774–782.
- DAC-2012-WeiSVLARHTKS #evaluation #named
- GLARE: global and local wiring aware routability evaluation (YW, CCNS, NV, ZL, CJA, LNR, ADH, GET, DK, SSS), pp. 768–773.
- DAC-2006-AlpertKSW
- Timing-driven Steiner trees are (practically) free (CJA, ABK, CCNS, QW), pp. 389–392.
- DAC-2006-HuAHKLSS #algorithm #performance
- Fast algorithms for slew constrained minimum cost buffering (SH, CJA, JH, SKK, ZL, WS, CCNS), pp. 308–313.
- DATE-2006-VenkataramanHLS #optimisation
- Integrated placement and skew optimization for rotary clocking (GV, JH, FL, CCNS), pp. 756–761.
- DAC-2005-LuSHZCHH #navigation #network
- Navigating registers in placement for clock network minimization (YL, CCNS, XH, QZ, YC, LH, JH), pp. 176–181.
- DAC-2005-SzeAHS
- Path based buffer insertion (CCNS, CJA, JH, WS), pp. 509–514.