Travelled to:6 × USA
Collaborated with:∅ H.Heeb P.K.W.Sr. T.A.Johnson P.Restle S.G.Walker S.Ponnapalli G.Goertzel B.J.Agule J.D.Lesser
Talks about:circuit (4) interconnect (2) analysi (2) system (2) electr (2) design (2) power (2) optim (2) model (2) logic (2)
Person: Albert E. Ruehli
DBLP: Ruehli:Albert_E=
Contributed to:
199919931992198119771973Wrote 8 papers:
- DAC-1999-RestleRW #design #performance
- Dealing with Inductance in High-Speed Chip Design (PR, AER, SGW), pp. 904–909.
- DAC-1993-HeebPR #modelling #using
- Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits (HH, SP, AER), pp. 702–706.
- DAC-1992-JohnsonR #feedback #parallel
- Parallel Waveform Relaxation of Circuits with Global Feedback Loops (TAJ, AER), pp. 12–15.
- DAC-1992-RuehliH #analysis #challenge
- Challenges and Advances in Electrical Interconnect Analysis (AER, HH), pp. 460–465.
- DAC-1981-Ruehli #analysis #logic #modelling #overview #scalability #simulation
- Survey of analysis, simulation and modeling for large scale logic circuits (AER), pp. 124–129.
- DAC-1977-AguleLRS #optimisation
- An experimental system for power/timing optimization of LSI chips (BJA, JDL, AER, PKWS), pp. 147–152.
- DAC-1977-RuehliSG #optimisation
- Analytical power/timing optimization technique for digital system (AER, PKWS, GG), pp. 142–146.
- DAC-1973-Ruehli #design #logic
- Electrical considerations in the computer aided design of logic circuit interconnections (AER), pp. 262–266.