Travelled to:1 × France
1 × USA
Collaborated with:R.Murgai S.M.Reddy T.Miyoshi M.B.Tahoori K.Hayashi T.Doi Y.Koyanagi O.Shiraki N.Imamura T.Shimizu H.Ishihata T.Shindo
Talks about:architectur (1) methodolog (1) substrat (1) parallel (1) interfac (1) support (1) analysi (1) sensit (1) compil (1) model (1)
Person: Takeshi Horie
DBLP: Horie:Takeshi
Contributed to:
2004
1994Wrote 2 papers:
- DATE-v1-2004-MurgaiRMHT #analysis #modelling
- Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis (RM, SMR, TM, TH, MBT), pp. 610–615.
- ASPLOS-1994-HayashiDHKSISIS #architecture #compilation #interface
- AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler (KH, TD, TH, YK, OS, NI, TS, HI, TS), pp. 196–207.