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Travelled to:
3 × USA
4 × Germany
5 × France
Collaborated with:
F.Firouzi S.Kiamehr F.Oboril M.Ebrahimi H.Asadi F.Lombardi S.R.Nassif L.Chen M.Beste G.Asadi R.Seyyedi J.Ewert J.Huang T.H.Osiecki P.M.B.Rao A.Ahari B.Khaleghi R.Bishnoi S.Wang Y.Hara-Azumi V.Sridharan D.R.Kaeli M.Fazeli S.N.Ahmadian S.G.Miremadi R.Murgai S.M.Reddy T.Miyoshi T.Horie R.Baranowski C.Liu H.Wunderlich A.Evans E.Costenaro D.Alexandrescu J.Henkel L.Bauer N.Dutt P.Gupta M.Shafique N.Wehn
Talks about:
analysi (7) base (6) design (4) multipl (3) power (3) induc (3) event (3) error (3) soft (3) use (3)

Person: Mehdi Baradaran Tahoori

DBLP DBLP: Tahoori:Mehdi_Baradaran

Contributed to:

DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
DATE 20112011
DATE 20062006
DATE 20052005
DATE v1 20042004
DATE v2 20042004
DAC 20032003

Wrote 24 papers:

DATE-2015-BaranowskiFKLTW #online #predict
On-line prediction of NBTI-induced aging rates (RB, FF, SK, CL, MBT, HJW), pp. 589–592.
DATE-2015-OborilET #monitoring #online
High-resolution online power monitoring for modern microprocessors (FO, JE, MBT), pp. 265–268.
DAC-2014-ChenT #control flow #design
Reliability-aware Register Binding for Control-Flow Intensive Designs (LC, MBT), p. 6.
DAC-2014-KiamehrOTN #analysis #approach #fault
Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach (SK, THO, MBT, SRN), p. 6.
DAC-2014-RaoEST #multi #using
Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes (PMBR, ME, RS, MBT), p. 6.
DATE-2014-AhariAKT #architecture #configuration management #power management #using
A power-efficient reconfigurable architecture using PCM configuration technology (AA, HA, BK, MBT), pp. 1–6.
DATE-2014-BishnoiEOT #power management #symmetry #termination
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM (RB, ME, FO, MBT), pp. 1–6.
DATE-2014-EbrahimiETSCA #analysis #embedded #fault
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales (ME, AE, MBT, RS, EC, DA), pp. 1–6.
DATE-2014-KiamehrFET #design #library #standard
Aging-aware standard cell library design (SK, FF, ME, MBT), pp. 1–4.
DATE-2014-WangFOT #3d #reduction
P/G TSV planning for IR-drop reduction in 3D-ICs (SW, FF, FO, MBT), pp. 1–6.
DAC-2013-EbrahimiAT #analysis #approach #multi
A layout-based approach for multiple event transient analysis (ME, HA, MBT), p. 6.
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap
Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DATE-2013-FirouziKTN #analysis #runtime
Incorporating the impacts of workload-dependent runtime variations into timing analysis (FF, SK, MBT, SRN), pp. 1022–1025.
DATE-2013-Hara-AzumiFKT #process
Instruction-set extension under process variation and aging effects (YHA, FF, SK, MBT), pp. 182–187.
DATE-2013-OborilT #design #pipes and filters
MTTF-balanced pipeline design (FO, MBT), pp. 270–275.
DATE-2012-BesteT #analysis #robust #standard
Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells (MB, MBT), pp. 1609–1614.
NBTI mitigation by optimized NOP assignment and insertion (FF, SK, MBT), pp. 218–223.
DATE-2011-FazeliAMAT #estimation #fault #multi
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs) (MF, SNA, SGM, HA, MBT), pp. 70–75.
DATE-2006-AsadiSTK #analysis
Vulnerability analysis of L2 cache elements to single event upsets (HA, VS, MBT, DRK), pp. 1276–1281.
DATE-2005-AsadiT #estimation #probability
An Accurate SER Estimation Method Based on Propagation Probability (GA, MBT), pp. 306–307.
DATE-v1-2004-MurgaiRMHT #analysis #modelling
Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis (RM, SMR, TM, TH, MBT), pp. 610–615.
DATE-v2-2004-HuangTL #fault tolerance #programmable
Fault Tolerance of Programmable Switch Blocks (JH, MBT, FL), pp. 1358–1359.
DATE-v2-2004-TahooriL #automaton #design #quantum #testing
Testing of Quantum Dot Cellular Automata Based Designs (MBT, FL), pp. 1408–1409.
DAC-2003-Tahoori #satisfiability #testing #using
Using satisfiability in application-dependent testing of FPGA interconnects (MBT), pp. 678–681.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.