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Travelled to:
1 × USA
Collaborated with:
R.A.Bergamaschi A.Goel
Talks about:
core (3) processor (1) connect (1) system (1) formal (1) design (1) verif (1) local (1) arbit (1) chip (1)

Person: William R. Lee

DBLP DBLP: Lee:William_R=

Contributed to:

DAC 20002000

Wrote 2 papers:

DAC-2000-BergamaschiL #design #using
Designing systems-on-chip using cores (RAB, WRL), pp. 420–425.
DAC-2000-GoelL #verification
Formal verification of an IBM CoreConnect processor local bus arbiter core (AG, WRL), pp. 196–200.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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