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Travelled to:
3 × Germany
8 × USA
Collaborated with:
Y.Jiang W.R.Lee R.Compasano H.D.Patel S.K.Shukla S.Wang S.Malik D.A.Lobo A.Kuehlmann R.Camposano M.Payer F.Bacchini P.G.Paulin R.Pawate A.Bernstein R.Chandra M.Ben-Romdhane W.Rosenstiel F.Ghenassia T.Grötker M.Kawarabayashi M.C.v.Lier A.Mayer M.Meredith M.Milligan S.Swan
Talks about:
system (6) level (5) synthesi (4) design (4) use (4) behavior (3) path (3) high (3) analysi (2) tool (2)

Person: Reinaldo A. Bergamaschi

DBLP DBLP: Bergamaschi:Reinaldo_A=

Contributed to:

DATE 20062006
DATE 20052005
DAC 20042004
DAC 20032003
DATE 20032003
DAC 20002000
DAC 19991999
DAC 19951995
DAC 19921992
DAC 19911991
DAC 19901990

Wrote 11 papers:

DATE-2006-PatelSB #behaviour #design
Heterogeneous behavioral hierarchy for system level designs (HDP, SKS, RAB), pp. 565–570.
DATE-2005-RosenstielBGGKLMMMS #question #tool support
Is there a Market for SystemC Tools? (WR, RAB, FG, TG, MK, MCvL, AM, MM, MM, SS), p. 950.
DAC-2004-BacchiniPBPBCB #design #industrial
System level design: six success stories in search of an industry (FB, PGP, RAB, RP, AB, RC, MBR), pp. 349–350.
DAC-2003-BergamaschiJ #analysis
State-based power analysis for systems-on-chip (RAB, YJ), pp. 638–641.
DATE-2003-WangMB #embedded #integration #modelling
Modeling and Integration of Peripheral Devices in Embedded Systems (SW, SM, RAB), pp. 10136–10141.
DAC-2000-BergamaschiL #design #using
Designing systems-on-chip using cores (RAB, WRL), pp. 420–425.
DAC-1999-Bergamaschi #behaviour #graph #logic #network #synthesis
Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis (RAB), pp. 213–218.
DAC-1995-Bergamaschi #design #problem #question #tool support
Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? (RAB), pp. 674–677.
DAC-1992-BergamaschiLK #behaviour #optimisation #synthesis #using
Control Optimization in High-Level Synthesis Using Behavioral Don’t Cares (RAB, DAL, AK), pp. 657–661.
DAC-1991-BergamaschiCP #analysis #synthesis #using
Data-Path Synthesis Using Path Analysis (RAB, RC, MP), pp. 591–596.
DAC-1990-CompasanoB #algorithm #scheduling #synthesis #using
Synthesis Using Path-Based scheduling: algorithms and Exercises (RC, RAB), pp. 450–455.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.