Travelled to:1 × The Netherlands
2 × Italy
2 × USA
Collaborated with:A.Biere E.M.Clarke A.Cimatti J.H.Kukula R.F.Damiano R.Raimi P.Bjesse T.Stanion M.Fujita D.Wang P.Ho J.Long H.T.Ma
Talks about:symbol (3) model (3) check (3) bdds (3) properti (2) without (2) formal (2) use (2) sat (2) microprocessor (1)
Person: Yunshan Zhu
DBLP: Zhu:Yunshan
Contributed to:
2003
2001
19991999
1999Wrote 5 papers:
- SAT-2003-BjesseKDSZ #satisfiability
- Guiding SAT Diagnosis with Tree Decompositions (PB, JHK, RFD, TS, YZ), pp. 315–329.
- DAC-2001-WangHLKZMD #abstraction #hybrid #refinement #simulation #verification
- Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines (DW, PHH, JL, JHK, YZ, HKTM, RFD), pp. 35–40.
- CAV-1999-BiereCRZ #model checking #safety #using
- Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs (AB, EMC, RR, YZ), pp. 60–71.
- DAC-1999-BiereCCFZ #model checking #satisfiability #using
- Symbolic Model Checking Using SAT Procedures instead of BDDs (AB, AC, EMC, MF, YZ), pp. 317–320.
- TACAS-1999-BiereCCZ #model checking
- Symbolic Model Checking without BDDs (AB, AC, EMC, YZ), pp. 193–207.