Travelled to:4 × USA
Collaborated with:J.Cong Y.Fan G.Liu M.Tan S.Dai R.Zhao K.Hao G.Han W.Jiang
Talks about:synthesi (3) pipelin (3) effici (3) level (3) high (3) communic (2) interconnect (1) architectur (1) reconfigur (1) algorithm (1)
Person: Zhiru Zhang
DBLP: Zhang:Zhiru
Contributed to:
2015201420062004Wrote 6 papers:
- DAC-2015-LiuZ #configuration management #performance
- A reconfigurable analog substrate for highly efficient maximum flow computation (GL, ZZ), p. 6.
- DAC-2015-ZhaoTDZ #pipes and filters #synthesis
- Area-efficient pipelining for FPGA-targeted high-level synthesis (RZ, MT, SD, ZZ), p. 6.
- DAC-2014-DaiTHZ #pipes and filters #synthesis
- Flushing-Enabled Loop Pipelining for High-Level Synthesis (SD, MT, KH, ZZ), p. 6.
- DAC-2006-CongFHJZ #behaviour #communication
- Behavior and communication co-optimization for systems with sequential communication media (JC, YF, GH, WJ, ZZ), pp. 675–678.
- DAC-2006-CongZ #algorithm #performance #scheduling
- An efficient and versatile scheduling algorithm based on SDC formulation (JC, ZZ), pp. 433–438.
- DAC-2004-CongFZ #architecture #automation #pipes and filters #synthesis
- Architecture-level synthesis for automatic interconnect pipelining (JC, YF, ZZ), pp. 602–607.