13 papers:
DATE-2015-ChangD #analysis #model checking #modelling #using- May-happen-in-parallel analysis of ESL models using UPPAAL model checking (CWC, RD), pp. 1567–1570.
- DATE-2014-ChenHD #analysis #graph #modelling
- May-happen-in-parallel analysis based on segment graphs for safe ESL models (WC, XH, RD), pp. 1–6.
DAC-2013-SchurmansZALACW #architecture #automation #communication #modelling #using- Creation of ESL power models for communication architectures using automatic calibration (SS, DZ, DA, RL, GA, XC, LW), p. 58.
- DATE-2012-ChenHD #design #parallel #simulation
- Out-of-order parallel simulation for ESL design (WC, XH, RD), pp. 141–146.
- DATE-2012-RamboHS #consistency #memory management #multi #on the #verification
- On ESL verification of memory consistency for system-on-chip multiprocessing (EAR, OPH, LCVdS), pp. 9–14.
- DAC-2011-HsuLFWHHY #analysis #design #manycore #modelling #named
- PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs (CWH, JLL, SCF, CCW, SYH, WTH, JCY), pp. 47–52.
- DATE-2009-AhmedERCST #performance #pipes and filters #programmable #reduction
- Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor (SZA, JE, LR, JBC, GS, LT), pp. 184–189.
- DAC-2008-YagiRKHTMSDM #question
- ESL hand-off: fact or EDA fiction? (HY, WR, TK, EH, HT, MM, GS, ND, GM), pp. 310–312.
- DAC-2007-KoelblBP #equivalence #memory management #modelling
- Memory Modeling in ESL-RTL Equivalence Checking (AK, JRB, CP), pp. 205–209.
- DATE-2007-PatelS #abstraction
- Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL (HDP, SKS), pp. 279–284.
- DAC-2006-HosseiniPCUGB #design #question #standard #verification
- Building a standard ESL design and verification methodology: is it just a dream? (AH, AP, HTC, PU, EFG, SB), pp. 370–371.
- DATE-2006-ViehlSBR #analysis #design #modelling #performance #simulation #uml
- Formal performance analysis and simulation of UML/SysML models for ESL design (AV, TS, OB, WR), pp. 242–247.
- DAC-2005-BacchiniMDMPSEU #named
- ESL: building the bridge between systems to silicon (FB, DM, TD, PM, SAP, SS, SKE, PU), pp. 69–70.
