BibSLEIGH corpus
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Used together with:
sub (10)
deep (9)
bus (3)
test (3)
time (2)

Stem micron$ (all stems)

11 papers:

DATEDATE-2015-ZhangZCY #scalability
Exploiting DRAM restore time variations in deep sub-micron scaling (XZ, YZ, BRC, JY), pp. 477–482.
CASECASE-2007-SaeediKEMP #automation #process #self
Automation and yield of micron-scale self-assembly processes (ES, SSK, JRE, DRM, BAP), pp. 375–380.
DATEDATE-v1-2004-WongT #configuration management #encoding #power management
Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus (SKW, CYT), pp. 130–135.
A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology (SB, JMP, PM), pp. 1404–1405.
DATEDATE-v2-2004-MangoCWC #fault #testing
Pattern Selection for Testing of Deep Sub-Micron Timing Defects (MCTC, LCW, KTC), p. 160.
DACDAC-2001-HenkelL #adaptation #design #named #power management
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs (JH, HL), pp. 744–749.
DACDAC-2000-ChuengDRR #challenge
Test challenges for deep sub-micron technologies (KTC, SD, MR, KR), pp. 142–149.
DACDAC-1999-BanerjeeMSH #on the
On Thermal Effects in Deep Sub-Micron VLSI Interconnects (KB, AM, ALSV, CH), pp. 885–891.
DACDAC-1999-KhatriMBOS #layout #novel
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications (SPK, AM, RKB, RHJMO, ALSV), pp. 491–496.
DATEDATE-1998-BisdounisKGN #modelling
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices (LB, OGK, CEG, SN), pp. 729–735.
DATEEDTC-1997-Sachdev #testing
Deep sub-micron IDDQ testing: issues and solutions (MS), pp. 271–278.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.