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Travelled to:
1 × USA
2 × France
4 × Germany
Collaborated with:
L.Torres N.Azémard V.Lomné M.Robert A.Dehbaoui L.Vincent S.Lesecq E.Beigné G.Perin P.Benoit B.Lasbouygues R.Wilson A.Verle X.Michel D.Auvergne R.Soares N.Calazans L.Zussa K.Tobich J.Dutertre L.Guillaume-Sage J.Clédière A.Tria
Talks about:
analysi (3) voltag (3) temperatur (2) statist (2) against (2) power (2) electromagnet (1) preprocess (1) differenti (1) implement (1)

Person: Philippe Maurine

DBLP DBLP: Maurine:Philippe

Contributed to:

DATE 20142014
DAC 20122012
DATE 20122012
DATE 20102010
DATE 20092009
DATE 20072007
DATE 20052005

Wrote 7 papers:

DATE-2014-ZussaDTDMGCT #detection #fault #injection #performance
Efficiency of a glitch detector against electromagnetic fault injection (LZ, AD, KT, JMD, PM, LGS, JC, AT), pp. 1–6.
DAC-2012-LionelPSE #monitoring #statistics #testing
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring (LV, PM, SL, EB), pp. 994–999.
DATE-2012-PerinTBM #analysis #implementation
Amplitude demodulation-based EM analysis of different RSA implementations (GP, LT, PB, PM), pp. 1167–1172.
DATE-2010-LomneDMTR #analysis #difference #preprocessor #statistics
Differential Power Analysis enhancement with statistical preprocessing (VL, AD, PM, LT, MR), pp. 1301–1304.
DATE-2009-LomneMTRSC #evaluation #logic #robust
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA (VL, PM, LT, MR, RS, NC), pp. 634–639.
DATE-2007-LasbouyguesWAM #analysis
Temperature and voltage aware timing analysis: application to voltage drops (BL, RW, NA, PM), pp. 1012–1017.
DATE-2005-VerleMAMA #optimisation #power management #protocol
Low Power Oriented CMOS Circuit Optimization Protocol (AV, XM, NA, PM, DA), pp. 640–645.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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