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Travelled to:
1 × USA
3 × France
4 × Germany
Collaborated with:
R.Drechsler H.M.Le U.Kühne R.Wille V.Herdt G.W.Dueck F.Haedicke G.Fey H.M.L.0001 S.Frehse M.Diepenbeck J.Seiter M.Soeken
Talks about:
verif (3) coverag (2) system (2) symbol (2) formal (2) driven (2) design (2) simul (2) understand (1) intermedi (1)

Person: Daniel Große

DBLP DBLP: Gro=szlig=e:Daniel

Contributed to:

DAC 20132013
DATE 20132013
DATE 20122012
ICGT 20122012
DATE 20092009
DATE 20082008
DATE 20072007
DATE 20062006
CAV (2) 20162016

Wrote 10 papers:

DAC-2013-LeGHD #simulation #using #verification
Verifying SystemC using an intermediate verification language and symbolic simulation (HML, DG, VH, RD), p. 6.
DATE-2013-LeGD #design #fault #locality #scalability
Scalable fault localization for SystemC TLM designs (HML, DG, RD), pp. 35–38.
DATE-2012-HaedickeGD #metric #verification
A guiding coverage metric for formal verification (FH, DG, RD), pp. 617–622.
ICGT-2012-DrechslerDGKLSSW #development
Completeness-Driven Development (RD, MD, DG, UK, HML, JS, MS, RW), pp. 38–50.
DATE-2009-KuhneGD #analysis #comprehension #design
Property analysis and design understanding (UK, DG, RD), pp. 1246–1249.
DATE-2009-WilleGFDD #debugging #network
Debugging of Toffoli networks (RW, DG, SF, GWD, RD), pp. 1284–1289.
DATE-2008-WilleLDG #logic #quantifier #synthesis
Quantified Synthesis of Reversible Logic (RW, HML, GWD, DG), pp. 1015–1020.
DATE-2007-GrosseKD #bound #functional #model checking
Estimating functional coverage in bounded model checking (DG, UK, RD), pp. 1176–1181.
DATE-2006-FeyGD #verification
Avoiding false negatives in formal verification for protocol-driven blocks (GF, DG, RD), pp. 1225–1226.
CAV-2016-HerdtLGD #named #performance #simulation
ParCoSS: Efficient Parallelized Compiled Symbolic Simulation (VH, HML0, DG, RD), pp. 177–183.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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