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Travelled to:
1 × Czech Republic
1 × Italy
1 × Switzerland
1 × The Netherlands
1 × United Kingdom
5 × France
5 × Germany
5 × USA
Collaborated with:
R.Drechsler M.Soeken M.Gogolla P.Niemann F.Hilken N.Przigoda O.Keszocze D.Große G.W.Dueck M.Kuhlmann J.Seiter H.M.Le J.Stoppe Z.Sasanian D.M.Miller H.Kreowski S.Kuske U.Kühne T.Ho C.Osewold A.G.Ortiz J.Peters C.Hilken J.Peleska S.Frehse M.Diepenbeck
Talks about:
model (14) uml (11) ocl (10) revers (6) verif (6) synthesi (4) circuit (4) base (4) use (4) behavior (3)

Person: Robert Wille

DBLP DBLP: Wille:Robert

Contributed to:

DAC 20152015
DATE 20152015
MoDELS 20152015
DAC 20142014
TAP 20142014
DATE 20132013
DAC 20122012
DATE 20122012
ICGT 20122012
TOOLS Europe 20122012
DATE 20112011
TAP 20112011
DAC 20102010
DATE 20102010
ICGT 20102010
DAC 20092009
DATE 20092009
DATE 20082008
ICMT 20152015
MoDELS 20162016
ECMFA 20172017

Wrote 27 papers:

DAC-2015-PetersWPKD #constraints #modelling #representation #uml
A generic representation of CCSL time constraints for UML/MARTE models (JP, RW, NP, UK, RD), p. 6.
DATE-2015-NiemannHGW #formal method #generative #modelling
Assisted generation of frame conditions for formal models (PN, FH, MG, RW), pp. 309–312.
DATE-2015-StoppeWD #automation #design #locality
Automated feature localization for dynamically generated SystemC designs (JS, RW, RD), pp. 277–280.
MoDELS-2015-NiemannHGW #contract
Extracting frame conditions from operation contracts (PN, FH, MG, RW), pp. 266–275.
MoDELS-2015-PrzigodaHWPD #behaviour #concurrent #modelling #ocl #uml
Checking concurrent behavior in UML/OCL models (NP, CH, RW, JP, RD), pp. 176–185.
DAC-2014-KeszoczeWHD #synthesis
Exact One-pass Synthesis of Digital Microfluidic Biochips (OK, RW, TYH, RD), p. 6.
TAP-2014-HilkenNGW #behaviour #comparison #modelling #ocl #uml #verification
Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models (FH, PN, MG, RW), pp. 99–116.
DATE-2013-SeiterWSD #ocl #specification #uml #verification
Determining relevant model elements for the verification of UML/OCL specifications (JS, RW, MS, RD), pp. 1189–1192.
DATE-2013-WilleGSKD #modelling #towards #verification
Towards a generic verification methodology for system models (RW, MG, MS, MK, RD), pp. 1193–1196.
DAC-2012-SasanianWM #quantum #using
Realizing reversible circuits using a new class of quantum gates (ZS, RW, DMM), pp. 36–41.
DATE-2012-SoekenWD #invariant #modelling #ocl #uml
Eliminating invariants in UML/OCL models (MS, RW, RD), pp. 1142–1145.
DATE-2012-WilleDOO #automation #design #power management #synthesis #using
Automatic design of low-power encoders using reversible circuit synthesis (RW, RD, CO, AGO), pp. 1036–1041.
DATE-2012-WilleSD #consistency #debugging #modelling #ocl #uml
Debugging of inconsistent UML/OCL models (RW, MS, RD), pp. 1078–1083.
ICGT-2012-DrechslerDGKLSSW #development
Completeness-Driven Development (RD, MD, DG, UK, HML, JS, MS, RW), pp. 38–50.
TOOLS-EUROPE-2012-SoekenWD #behaviour #development #natural language #using
Assisted Behavior Driven Development Using Natural Language Processing (MS, RW, RD), pp. 269–287.
DATE-2011-SoekenWD #aspect-oriented #modelling #uml #verification
Verifying dynamic aspects of UML models (MS, RW, RD), pp. 1077–1082.
DATE-2011-WilleKD #scalability
Determining the minimal number of lines for large reversible circuits (RW, OK, RD), pp. 1204–1207.
TAP-2011-SoekenWD #data type #encoding #modelling #ocl #satisfiability #uml #verification
Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models (MS, RW, RD), pp. 152–170.
DAC-2010-WilleSD
Reducing the number of lines in reversible circuits (RW, MS, RD), pp. 647–652.
DATE-2010-SoekenWKGD #modelling #ocl #satisfiability #uml #using #verification
Verifying UML/OCL models using Boolean satisfiability (MS, RW, MK, MG, RD), pp. 1341–1344.
ICGT-2010-KreowskiKW #graph transformation #satisfiability
Graph Transformation Units Guided by a SAT Solver (HJK, SK, RW), pp. 27–42.
DAC-2009-WilleD #logic #scalability #synthesis
BDD-based synthesis of reversible logic for large functions (RW, RD), pp. 270–275.
DATE-2009-WilleGFDD #debugging #network
Debugging of Toffoli networks (RW, DG, SF, GWD, RD), pp. 1284–1289.
DATE-2008-WilleLDG #logic #quantifier #synthesis
Quantified Synthesis of Reversible Logic (RW, HML, GWD, DG), pp. 1015–1020.
ICMT-2015-HilkenNGW #concept #modelling #ocl #uml #validation #verification
From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification (FH, PN, MG, RW), pp. 149–165.
MoDELS-2016-PrzigodaWD #ocl #performance #smt
Ground setting properties for an efficient translation of OCL in SMT-based model finding (NP, RW, RD), pp. 261–271.
ECMFA-2017-GogollaHNW #diagrams #independence #uml #verification
Formulating Model Verification Tasks Prover-Independently as UML Diagrams (MG, FH, PN, RW), pp. 232–247.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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