Travelled to:1 × France
2 × USA
Collaborated with:A.J.Strojwas K.Brock C.Edwards R.Lannoo U.Schlichtmann A.Domic D.Overhauser M.Kliment
Talks about:time (3) design (2) verif (2) power (2) construct (1) synthesi (1) strategi (1) interact (1) perform (1) signal (1)
Person: Jacques Benkoski
DBLP: Benkoski:Jacques
Contributed to:
2002
19911989Wrote 3 papers:
- DATE-2002-BrockELSDBOK #design #power management
- Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs (KB, CE, RL, US, AD, JB, DO, MK), p. 538.
- DAC-1991-BenkoskiS #layout #synthesis #verification
- The Role of Timing Verification in Layout Synthesis (JB, AJS), pp. 612–619.
- DAC-1989-BenkoskiS #interactive #modelling #multi #verification
- Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator (JB, AJS), pp. 668–673.