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Travelled to:
1 × France
5 × USA
Collaborated with:
V.D.Agrawal T.J.Chakraborty D.R.Brasen J.Giraldi X.Chen S.W.Director K.Heragu S.T.Chakradhar S.Parikh J.Sienicki G.Ramakrishnan
Talks about:
generat (3) automat (3) fault (3) delay (3) test (3) sequenti (2) circuit (2) design (2) ulyss (2) estim (2)

Person: Michael L. Bushnell

DBLP DBLP: Bushnell:Michael_L=

Contributed to:

DAC 19941994
EDAC-ETC-EUROASIC 19941994
DAC 19931993
DAC 19921992
DAC 19901990
DAC 19881988
DAC 19861986

Wrote 9 papers:

DAC-1994-HeraguBA #fault #performance
An Efficient Path Delay Fault Coverage Estimator (KH, MLB, VDA), pp. 516–521.
EDAC-1994-ParikhSBSG #automation #design #distributed #fault #framework
Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework (SP, MLB, JS, GR), pp. 610–617.
DAC-1993-ChakrabortyAB #design #fault #testing
Design for Testability for Path Delay faults in Sequential Circuits (TJC, VDA, MLB), pp. 453–457.
DAC-1992-ChakrabortyAB #fault #generative #logic #modelling #random #testing
Delay Fault Models and Test Generation for Random Logic Sequential Circuits (TJC, VDA, MLB), pp. 165–172.
DAC-1990-BrasenB #algorithm #named #optimisation
MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing (DRB, MLB), pp. 107–110.
DAC-1990-ChakradharAB #automation #generative #polynomial #programming #testing #using
Automatic Test Generation Using Quadratic 0-1 Programming (STC, VDA, MLB), pp. 654–659.
DAC-1990-GiraldiB #automation #future of #generative #named
EST: The New Frontier in Automatic Test-Pattern Generation (JG, MLB), pp. 667–672.
DAC-1988-ChenB #layout
A Module Area Estimator for VLSI Layout (XC, MLB), pp. 54–59.
DAC-1986-BushnellD #integration #tool support #using
VLSI CAD tool integration using the Ulysses environment (MLB, SWD), pp. 55–61.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.