Travelled to:1 × China
1 × France
1 × Mexico
1 × Spain
10 × USA
Collaborated with:D.J.Palframan N.S.Kim J.E.Smith I.Kim J.F.Cantin S.Franey D.Gope A.Nere A.Hashmi L.Su K.M.Lepak M.Hayenga V.R.K.Naresh D.Vantrease N.L.Binkert C.B.Wilkerson J.P.Shen G.Tononi J.J.Thomas N.Aggarwal S.Hu H.W.Cain R.Rajwar M.Marden
Talks about:effici (4) processor (3) architectur (2) neuron (2) simpl (2) power (2) error (2) coher (2) valu (2) atom (2)
Person: Mikko H. Lipasti
DBLP: Lipasti:Mikko_H=
Contributed to:
201520142013
2011
2011201120082006
200620062004200220011996Wrote 17 papers:
- HPCA-2015-FraneyL
- Tag tables (SF, MHL), pp. 514–525.
- HPCA-2015-PalframanKL #energy #fault #named #performance
- iPatch: Intelligent fault patching to improve energy efficiency (DJP, NSK, MHL), pp. 428–438.
- HPCA-2014-GopeL
- Atomic SC for simple in-order processors (DG, MHL), pp. 404–415.
- HPCA-2014-HayengaNL #architecture #execution #named #performance
- Revolver: Processor architecture for power efficient loop execution (MH, VRKN, MHL), pp. 591–602.
- HPCA-2014-PalframanKL #fault
- Precision-aware soft error protection for GPUs (DJP, NSK, MHL), pp. 49–59.
- HPCA-2013-NereHLT #behaviour #biology #semantic gap
- Bridging the semantic gap: Emulating biological neuronal behaviors with simple digital neurons (AN, AH, MHL, GT), pp. 472–483.
- ASPLOS-2011-HashmiNTL
- A case for neuromorphic ISAs (AH, AN, JJT, MHL), pp. 145–158.
- DATE-2011-PalframanKL #detection #fault #low cost
- Time redundant parity for low-cost transient error detection (DJP, NSK, MHL), pp. 52–57.
- HPCA-2011-VantreaseLB #protocol
- Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocols (DV, MHL, NLB), pp. 132–143.
- HPCA-2008-AggarwalCLS #power management
- Power-Efficient DRAM Speculation (NA, JFC, MHL, JES), pp. 317–328.
- ASPLOS-2006-CantinLS
- Stealth prefetching (JFC, MHL, JES), pp. 274–282.
- CGO-2006-SuL
- Dynamic Class Hierarchy Mutation (LS, MHL), pp. 98–110.
- HPCA-2006-HuKLS #approach #implementation #performance
- An approach for implementing efficient superscalar CISC processors (SH, IK, MHL, JES), pp. 41–52.
- HPCA-2004-KimL #comprehension #scheduling
- Understanding Scheduling Replay Schemes (IK, MHL), pp. 198–209.
- ASPLOS-2002-LepakL
- Temporally silent stores (KML, MHL), pp. 30–41.
- HPCA-2001-CainRML #architecture #evaluation #java
- An Architectural Evaluation of Java TPC-W (HWC, RR, MM, MHL), pp. 229–240.
- ASPLOS-1996-LipastiWS #locality #predict
- Value Locality and Load Value Prediction (MHL, CBW, JPS), pp. 138–147.