Travelled to:1 × France
2 × USA
3 × Germany
Collaborated with:R.Leupers H.Meyr G.Braun A.Nohl G.Ascheid A.Hoffmann A.Chattopadhyay D.Kammler E.M.Witte A.Wieferink V.Greive M.Steinert B.Geukes H.Ishebabi L.Fanucci M.Cassiano S.Saponara
Talks about:processor (4) architectur (3) synthesi (3) explor (3) instruct (2) implement (1) techniqu (1) hierarch (1) abstract (1) univers (1)
Person: Oliver Schliebusch
DBLP: Schliebusch:Oliver
Contributed to:
200620062004
200320032002Wrote 6 papers:
- DATE-2006-ChattopadhyayGKWSILAM #automation #embedded
- Automatic ADL-based operand isolation for embedded processors (AC, BG, DK, EMW, OS, HI, RL, GA, HM), pp. 600–605.
- DATE-DF-2006-FanucciCSKWSALM #design #image #linear #synthesis
- ASIP design and synthesis for non linear filtering in image processing (LF, MC, SS, DK, EMW, OS, GA, RL, HM), pp. 233–238.
- DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation #synthesis
- RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.
- DAC-2003-NohlGBALSM #architecture #encoding #modelling #synthesis #using
- Instruction encoding synthesis for architecture exploration using hierarchical processor models (AN, VG, GB, AH, RL, OS, HM), pp. 262–267.
- DATE-2003-BraunWSLMN #abstraction #memory management #multi
- Processor/Memory Co-Exploration on Multiple Abstraction Levels (GB, AW, OS, RL, HM, AN), pp. 10966–10973.
- DAC-2002-NohlBSLMH #architecture #flexibility #performance #simulation
- A universal technique for fast and flexible instruction-set architecture simulation (AN, GB, OS, RL, HM, AH), pp. 22–27.