BibSLEIGH — Rainer

Travelled to:

1 × Poland
10 × Germany
10 × USA
9 × France

Collaborated with:

G.Ascheid H.Meyr ∅ A.Nohl K.Karuri G.Braun S.Kraemer P.Marwedel O.Schliebusch J.Castrillón M.Hohenauer J.Ceng A.Chattopadhyay H.Scharwächter L.G.Murillo T.Kogel J.F.Eusse J.Wagner S.Bashford L.Ladage A.Hoffmann W.Sheng D.Kammler J.Jovic S.Yakoushkin A.Basu X.Chen G.Martin F.Schirrmeister T.Kempf A.Wieferink T.Isshiki H.Ishebabi L.Thiele O.Wahlen A.Tretter M.Pandey L.Fanucci E.M.Witte S.Wawroschek J.H.Weinstock C.Schumacher L.Tosoratto W.Verachtert T.Ashby A.Vandecappelle M.Kedia P.Sudowe B.Leibe T.Sadasue L.Eeckhout N.P.Topham X.Nie B.Kienhuis M.Weiss A.Vajda M.Bekooij S.Ha R.Dömer L.Gao X.Chen F.Angiolini F.Ferrari C.Ferri L.Benini S.Wallentowitz M.A.A.Faruque T.Glökler M.Odendahl A.Goens B.Ries B.Vöcking T.Henriksson S.Schürmans D.Zhang D.Auras L.Wang R.Plyaskin A.Herkersdorf M.Vaupel F.Engel G.Bette B.Singh W.Ahmed M.Doerper B.Vanthournout V.Greive N.Wehn M.Roodzant J.Stahl A.Cohen B.Janson R.Velasquez A.Stulova M.Steinert H.Kunieda B.Geukes M.Cassiano S.Saponara L.Schor B.H.H.Juurlink M.A.Mesa A.Pohl R.Jessenberger V.Reyes H.v.Someren

Talks about:

processor (17) design (10) code (9) architectur (8) platform (7) explor (7) applic (7) mpsoc (7) use (7) instruct (6)

Person: Rainer Leupers

DBLP: Leupers:Rainer

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1993

Wrote 48 papers:

DATE-2015-CastrillonTSSJA #manycore #programming #question: Multi/many-core programming: where are we standing? (JC, LT, LS, WS, BHHJ, MAM, AP, RJ, VR, RL), pp. 1708–1717.
DATE-2014-EusseLASLS #architecture #component #embedded #flexibility: A flexible ASIP architecture for connected components labeling in embedded vision applications (JFE, RL, GA, PS, BL, TS), pp. 1–6.
DATE-2014-LeupersWLRSFCJ #towards: Technology transfer towards Horizon 2020 (RL, NW, RL, MR, JS, LF, AC, BJ), p. 1.
DATE-2014-MurilloWCLA #automation #concurrent #constraints #debugging #detection: Automatic detection of concurrency bugs through event ordering constraints (LGM, SW, JC, RL, GA), pp. 1–6.
DATE-2014-OdendahlGLARVH #manycore: Optimized buffer allocation in multicore platforms (MO, AG, RL, GA, BR, BV, TH), pp. 1–6.
DATE-2014-WeinstockSLAT #parallel #simulation: Time-decoupled parallel SystemC simulation (JHW, CS, RL, GA, LT), pp. 1–4.
DAC-2013-SchurmansZALACW #architecture #automation #communication #modelling #using: Creation of ESL power models for communication architectures using automatic calibration (SS, DZ, DA, RL, GA, XC, LW), p. 58.
DAC-2012-CastrillonTLA: Communication-aware mapping of KPN applications onto heterogeneous MPSoCs (JC, AT, RL, GA), pp. 1266–1271.
DAC-2012-MurilloEJYLA #hybrid #simulation: Synchronization for hybrid MPSoC full-system simulation (LGM, JFE, JJ, SY, RL, GA), pp. 121–126.
DATE-2012-JovicYMELA #hybrid #simulation: Hybrid simulation for extensible processor cores (JJ, SY, LGM, JFE, RL, GA), pp. 288–291.
DATE-2012-LeupersMPHSKV #platform: Virtual platforms: Breaking new grounds (RL, GM, RP, AH, FS, TK, MV), pp. 685–690.
DATE-2011-LeupersEMSTC #manycore #towards: Virtual Manycore platforms: Moving towards 100+ processor cores (RL, LE, GM, FS, NPT, XC), pp. 715–720.
DATE-2010-CastrillonVSSCLAM #analysis: Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms (JC, RV, AS, WS, JC, RL, GA, HM), pp. 753–758.
DATE-2010-LeupersTNKWI #programming: Cool MPSoC programming (RL, LT, XN, BK, MW, TI), pp. 1488–1493.
DATE-2009-LeupersVBHDN #exclamation #programming: Programming MPSoC platforms: Road works ahead! (RL, AV, MB, SH, RD, AN), pp. 1584–1589.
DAC-2008-CengCSSLAMIK #framework #named #parallel: MAPS: an integrated framework for MPSoC application parallelization (JC, JC, WS, HS, RL, GA, HM, TI, HK), pp. 754–759.
DAC-2008-GaoKKLAM #estimation #hybrid #multi #performance #simulation #using: Multiprocessor performance estimation using hybrid simulation (LG, KK, SK, RL, GA, HM), pp. 325–330.
DATE-2008-ChattopadhyayCILAM #architecture #configuration management #modelling: High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures (AC, XC, HI, RL, GA, HM), pp. 1334–1339.
DATE-2008-HohenauerELAMBS #execution #optimisation: Retargetable Code Optimization for Predicated Execution (MH, FE, RL, GA, HM, GB, BS), pp. 1492–1497.
DATE-2008-LeupersAVAV #architecture #design #multi: System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures (RL, GA, WV, TA, AV).
DATE-2007-ChattopadhyayAKKLAM #configuration management #design #embedded: Design space exploration of partially re-configurable embedded processors (AC, WA, KK, DK, RL, GA, HM), pp. 319–324.
DATE-2007-KraemerLAM #interactive #parallel #program transformation #source code #using: Interactive presentation: SoftSIMD — exploiting subword parallelism using source code transformations (SK, RL, GA, HM), pp. 1349–1354.
DATE-2006-AngioliniCLFFB #design #framework: An integrated open framework for heterogeneous MPSoC design space exploration (FA, JC, RL, FF, CF, LB), pp. 1145–1150.
DATE-2006-ChattopadhyayGKWSILAM #automation #embedded: Automatic ADL-based operand isolation for embedded processors (AC, BG, DK, EMW, OS, HI, RL, GA, HM), pp. 600–605.
DATE-2006-KempfKWALM #estimation #fine-grained #framework #performance #using: A SW performance estimation framework for early system-level-design using fine-grained instrumentation (TK, KK, SW, GA, RL, HM), pp. 468–473.
DATE-2006-LeupersKKP #configuration management #design #embedded #set #synthesis: A design flow for configurable embedded processors based on optimized instruction set extension synthesis (RL, KK, SK, MP), pp. 581–586.
DATE-2006-ScharwachterHLAM #hardware #interprocedural #multi #network #optimisation #thread #using: An interprocedural code optimization technique for network processors using hardware multi-threading support (HS, MH, RL, GA, HM), pp. 919–924.
DATE-DF-2006-FanucciCSKWSALM #design #image #linear #synthesis: ASIP design and synthesis for non linear filtering in image processing (LF, MC, SS, DK, EMW, OS, GA, RL, HM), pp. 233–238.
DATE-DF-2006-KaruriLAMK #composition #design #float #implementation: Design and implementation of a modular and portable IEEE 754 compliant floating-point unit (KK, RL, GA, HM, MK), pp. 221–226.
DAC-2005-KaruriFKLAM #design #fine-grained #profiling #source code: Fine-grained application source code profiling for ASIP design (KK, MAAF, SK, RL, GA, HM), pp. 329–334.
DATE-2005-CengHLAMB #c #compilation #modelling #semantics: C Compiler Retargeting Based on Instruction Semantics Models (JC, MH, RL, GA, HM, GB), pp. 1150–1155.
DATE-2005-KempfDLAMKV #composition #framework #multi #simulation: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms (TK, MD, RL, GA, HM, TK, BV), pp. 876–881.
DAC-2004-BraunNSCHSLM #approach #consistency #design #flexibility #novel: A novel approach for flexible and consistent ADL-driven ASIP design (GB, AN, WS, JC, MH, HS, RL, HM), pp. 717–722.
DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation #synthesis: RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.
DATE-v2-2004-HohenauerSKWKLAMBS #c #compilation #generative #modelling: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models (MH, HS, KK, OW, TK, RL, GA, HM, GB, HvS), pp. 1276–1283.
DATE-v2-2004-WieferinkKLAMBN #communication #framework #multi: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform (AW, TK, RL, GA, HM, GB, AN), pp. 1256–1263.
CC-2003-Leupers #algorithm #evaluation #optimisation: Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms (RL), pp. 290–302.
DAC-2003-NohlGBALSM #architecture #encoding #modelling #synthesis #using: Instruction encoding synthesis for architecture exploration using hierarchical processor models (AN, VG, GB, AH, RL, OS, HM), pp. 262–267.
DATE-2003-BraunWSLMN #abstraction #memory management #multi: Processor/Memory Co-Exploration on Multiple Abstraction Levels (GB, AW, OS, RL, HM, AN), pp. 10966–10973.
DAC-2002-NohlBSLMH #architecture #flexibility #performance #simulation: A universal technique for fast and flexible instruction-set architecture simulation (AN, GB, OS, RL, HM, AH), pp. 22–27.
LCTES-SCOPES-2002-WahlenGNHLM #architecture #case study #compilation: Application specific compiler/architecture codesign: a case study (OW, TG, AN, AH, RL, HM), pp. 185–193.
LCTES-OM-2001-WagnerL #c #compilation #design #industrial #network: C Compiler Design for an Industrial Network Processor (JW, RL), pp. 155–164.
DATE-2000-Leupers: Code Selection for Media Processors with SIMD Instructions (RL), pp. 4–8.
DAC-1999-BashfordL #constraints #fixpoint: Constraint Driven Code Selection for Fixed-Point DSPs (SB, RL), pp. 817–822.
DATE-1999-Leupers #code generation #embedded: Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors (RL), p. 105–?.
DATE-1998-BasuLM #source code: Register-Constrained Address Computation in DSP Programs (AB, RL, PM), pp. 929–930.
EDTC-1997-LeupersM #generative #modelling: Retargetable generation of code selectors from HDL processor models (RL, PM), pp. 140–144.
DAC-1993-LadageL #algorithm #using: Resistance Extraction using a Routing Algorithm (LL, RL), pp. 38–42.