BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
2 × France
2 × Germany
2 × USA
Collaborated with:
F.Catthoor D.Verkest A.Lambrechts M.Jayapala M.Hartmann D.Novo M.Li R.Fasthuber T.Gemmeke M.M.Sabry J.Stuijt D.Atienza M.Komalan J.I.G.Perez C.Tenllado P.Agrawal N.Sharma L.V.d.Perre H.Corporaal S.Khan I.Agbo S.Hamdioui H.Kukner B.Kaczer I.Karageorgos M.Stucchi J.Ryckaert Z.Tokei R.Baert S.Sakhare W.Dehaene
Talks about:
architectur (2) processor (2) thread (2) regist (2) explor (2) multi (2) sram (2) base (2) interconnect (1) temperatur (1)

Person: Praveen Raghavan

DBLP DBLP: Raghavan:Praveen

Contributed to:

DATE 20152015
DATE 20142014
DAC 20132013
DAC 20102010
DATE 20072007
DATE 20062006

Wrote 8 papers:

DATE-2015-KarageorgosSRRT #multi #variability
Impact of interconnect multiple-patterning variability on SRAMs (IK, MS, PR, JR, ZT, DV, RB, SS, WD), pp. 609–612.
DATE-2014-GemmekeSSRCA #memory management
Resolving the memory bottleneck for single supply near-threshold computing (TG, MMS, JS, PR, FC, DA), pp. 1–6.
DATE-2014-KhanAHKKRC #analysis #bias
Bias Temperature Instability analysis of FinFET based SRAM cells (SK, IA, SH, HK, BK, PR, FC), pp. 1–6.
DATE-2014-KomalanPTRHC
Feasibility exploration of NVM based I-cache through MSHR enhancements (MK, JIGP, CT, PR, MH, FC), pp. 1–6.
DAC-2013-AgrawalRHSPC #architecture #clustering #framework #multi #platform
Early exploration for platform architecture instantiation with multi-mode application partitioning (PA, PR, MH, NS, LVdP, FC), p. 8.
DAC-2010-NovoLFRC #data flow #finite #precise
Exploiting finite precision information to guide data-flow mapping (DN, ML, RF, PR, FC), pp. 248–253.
DATE-2007-RaghavanLJCVC #embedded #power management #symmetry
Very wide register: an asymmetric register file organization for low power embedded processors (PR, AL, MJ, FC, DV, HC), pp. 1066–1071.
DATE-2006-RaghavanLJCV #architecture #distributed #multi #thread
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors (PR, AL, MJ, FC, DV), pp. 339–344.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.