Travelled to:1 × Canada
1 × Germany
5 × USA
Collaborated with:R.K.Brayton T.R.Shiple A.L.Sangiovanni-Vincentelli C.Coelho S.Skalberg J.H.Kukula V.Singhal F.Somenzi J.V.Sanghavi A.Aziz S.Cheng D.L.Dill N.James S.Rawat G.Berry L.Fix H.Foster G.Stålmarck C.Widdoes F.Balarin R.Hojati T.Kam S.C.Krishnan S.Tasiran H.Wang G.D.Hachtel S.A.Edwards S.P.Khatri Y.Kukimoto A.Pardo S.Qadeer S.Sarwary G.Swamy T.Villa
Talks about:verif (5) formal (3) bdd (2) hiercharchi (1) comparison (1) synthesi (1) sequenti (1) reachabl (1) presburg (1) perform (1)
Person: Rajeev K. Ranjan
DBLP: Ranjan:Rajeev_K=
Contributed to:
20092002
1999
1998199619961994Wrote 7 papers:
- DAC-2009-RanjanCS #debugging #verification
- Beyond verification: leveraging formal for debugging (RKR, CC, SS), pp. 648–651.
- DAC-2002-DillJRBFFRSW #verification
- Formal verification methods: getting around the brick wall (DLD, NJ, SR, GB, LF, HF, RKR, GS, CW), pp. 576–577.
- DATE-1999-RanjanSSB #using #verification
- Using Combinational Verification for Sequential Circuits (RKR, VS, FS, RKB), pp. 138–144.
- CAV-1998-ShipleKR #comparison #reachability
- A Comparison of Presburger Engines for EFSM Reachability (TRS, JHK, RKR), pp. 280–292.
- CAV-1996-BraytonHSSACEKKPQRSSSV #named #synthesis #verification
- VIS: A System for Verification and Synthesis (RKB, GDH, ALSV, FS, AA, STC, SAE, SPK, YK, AP, SQ, RKR, SS, TRS, GS, TV), pp. 428–432.
- DAC-1996-SanghaviRBS #memory management #performance
- High Performance BDD Package By Exploiting Memory Hiercharchy (JVS, RKR, RKB, ALSV), pp. 635–640.
- DAC-1994-AzizBCHKKRSSTWBS #named #verification
- HSIS: A BDD-Based Environment for Formal Verification (AA, FB, STC, RH, TK, SCK, RKR, TRS, VS, ST, HYW, RKB, ALSV), pp. 454–459.