Travelled to:1 × France
1 × Germany
2 × USA
Collaborated with:Y.Liu H.Yang Y.Xie Yu Ji 0002 Xinfeng Xie Y.Wang X.He X.S.Hu X.Li K.Ma Y.Liu D.Zhang B.Sai M.Chiang Youyang Zhang Peiqi Wang 0001 Xing Hu 0001 Youhui Zhang Y.X.0001 Y.Zheng K.Swaminathan J.Sampson V.Narayanan X.Hu Ling Liang Lei Deng 0003 Pengfei Zuo Y.Ding C.Liu T.Sherwood Z.Li H.Li M.Chang S.John J.Shu
Talks about:architectur (4) nonvolatil (3) processor (3) base (3) harvest (2) ambient (2) system (2) energi (2) reconfigur (1) framework (1)
Person: Shuangchen Li
DBLP: Li:Shuangchen
Contributed to:
2015
2015
20132012
20192020Wrote 6 papers:
- DAC-2015-LiuLLWLMLCJ0SY #energy
- Ambient energy harvesting nonvolatile processors: from circuit to system (YL, ZL, HL, YW, XL, KM, SL, MFC, SJ, YX, JS, HY), p. 6.
- HPCA-2015-MaZLSLLS0N #architecture #energy
- Architecture exploration for ambient energy harvesting nonvolatile processors (KM, YZ, SL, KS, XL, YL, JS, YX, VN), pp. 526–537.
- DATE-2013-HeLLHY #streaming #synthesis
- Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications (XH, SL, YL, XSH, HY), pp. 992–995.
- DATE-2012-WangLLZLSCY #architecture
- A compression-based area-efficient recovery architecture for nonvolatile processors (YW, YL, YL, DZ, SL, BS, MFC, HY), pp. 1519–1524.
- ASPLOS-2019-JiZXLWHZX #architecture #configuration management #named #stack
- FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture (YJ0, YZ, XX, SL, PW0, XH0, YZ, YX0), pp. 733–747.
- ASPLOS-2020-HuLL0Z0XDLSX #architecture #framework #learning #named
- DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints (XH, LL, SL, LD0, PZ, YJ0, XX, YD, CL, TS, YX), pp. 385–399.