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Travelled to:
1 × France
1 × Italy
1 × The Netherlands
19 × USA
3 × Canada
Collaborated with:
C.Chambers M.Philipose M.Mock D.R.Kerns H.M.Levy A.Shoshani J.L.Lo J.Redstone D.G.Bradlee R.R.Henry B.Grant T.E.Jeremiassen R.Thekkath R.H.Katz E.G.Sirer L.McDowell S.D.Gribble E.J.Koldinger J.S.Chase F.Olken B.N.Bershad O.Anderson E.Fortuna L.Ceze D.C.Atkinson M.Das D.M.Tullsen J.Aldrich J.Auslander M.Mercaldi S.Swanson A.Petersen A.Putnam A.Schwerin M.Oskin S.Savage P.Pardyak M.E.Fiuczynski D.Becker
Talks about:
schedul (8) instruct (6) architectur (4) processor (4) support (4) program (4) system (4) compil (4) optim (4) time (4)

Person: Susan J. Eggers

DBLP DBLP: Eggers:Susan_J=

Facilitated 2 volumes:

ASPLOS 2008Ed
ASPLOS 1996Ed

Contributed to:

HPCA 20112011
PLDI 20102010
ASPLOS 20062006
HPCA 20032003
PPoPP 20032003
FSE 20022002
POPL 20022002
PASTE 20012001
ASPLOS 20002000
Best of PLDI 20041999
HPCA 19991999
PLDI 19991999
SAS 19991999
PEPM 19971997
PLDI 19961996
PLDI 19951995
PPoPP 19951995
SOSP 19951995
ASPLOS 19941994
Best of PLDI 20041993
PLDI 19931993
ASPLOS 19921992
ASPLOS 19911991
PLDI 19911991
ASPLOS 19891989
VLDB 19811981
VLDB 19801980

Wrote 27 papers:

HPCA-2011-AndersonFCE #architecture #javascript #mobile
Checked Load: Architectural support for JavaScript type-checking on mobile processors (OA, EF, LC, SJE), pp. 419–430.
PLDI-2010-Eggers
2010 Athena lecture (SJE), p. 98.
ASPLOS-2006-MercaldiSPPSOE #architecture #data flow #scheduling
Instruction scheduling for a tiled dataflow architecture (MM, SS, AP, AP, AS, MO, SJE), pp. 141–150.
HPCA-2003-RedstoneEL #named #smt #thread
Mini-Threads: Increasing TLP on Small-Scale SMT Processors (JR, SJE, HML), pp. 19–30.
PPoPP-2003-McDowellEG #parallel #thread
Improving server software support for simultaneous multithreaded processors (LM, SJE, SDG), pp. 37–48.
FSE-2002-MockACE #points-to #slicing
Improving program slicing with dynamic points-to data (MM, DCA, CC, SJE), pp. 71–80.
POPL-2002-PhiliposeCE #automation #compilation #staged #towards
Towards automatic construction of staged compilers (MP, CC, SJE), pp. 113–125.
PASTE-2001-MockDCE #analysis #comparison #comprehension #optimisation #points-to #set
Dynamic points-to sets: a comparison with static analyses and potential applications in program understanding and optimization (MM, MD, CC, SJE), pp. 66–72.
ASPLOS-2000-RedstoneEL #analysis #architecture #behaviour #operating system #parallel #thread
An Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture (JR, SJE, HML), pp. 245–256.
Best-of-PLDI-1999-GrantPMCE99a #evaluation #optimisation #runtime #staged
An evaluation of staged run-time optimizations in DyC (with retrospective) (BG, MP, MM, CC, SJE), pp. 656–669.
HPCA-1999-TullsenLEL #fine-grained #multi #thread
Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor (DMT, JLL, SJE, HML), pp. 54–58.
PLDI-1999-GrantPMCE #evaluation #optimisation #runtime #staged
An Evaluation of Staged Run-Time Optimizations in DyC (BG, MP, MM, CC, SJE), pp. 293–304.
SAS-1999-AldrichCSE #analysis #java #source code
Static Analyses for Eliminating Unnecessary Synchronization from Java Programs (JA, CC, EGS, SJE), pp. 19–38.
PEPM-1997-GrantMPCE #c #runtime
Annotation-Directed Run-Time Specialization in C (BG, MM, MP, CC, SJE), pp. 163–178.
PLDI-1996-AuslanderPCEB #compilation #effectiveness #performance
Fast, Effective Dynamic Compilation (JA, MP, CC, SJE, BNB), pp. 149–159.
PLDI-1995-LoE #compilation #optimisation #parallel #scheduling
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism (JLL, SJE), pp. 151–162.
PPoPP-1995-JeremiassenE #data transformation #memory management #multi
Reducing False Sharing on Shared Memory Multiprocessors through Compile Time Data Transformations (TEJ, SJE), pp. 179–188.
SOSP-1995-BershadSPSFBCE #operating system #performance #safety
Extensibility, Safety and Performance in the SPIN Operating System (BNB, SS, PP, EGS, MEF, DB, CC, SJE), pp. 267–284.
ASPLOS-1994-ThekkathE #effectiveness #hardware #multi
The Effectiveness of Multiple Hardware Contexts (RT, SJE), pp. 328–337.
Best-of-PLDI-1993-KernsE93a #latency #memory management #nondeterminism #scheduling
Balanced scheduling: instruction scheduling when memory latency is uncertain (with retrospective) (DRK, SJE), pp. 515–527.
PLDI-1993-KernsE #latency #memory management #nondeterminism #scheduling
Balanced Scheduling: Instruction Scheduling When Memory Latency is Uncertain (DRK, SJE), pp. 278–289.
ASPLOS-1992-KoldingerCE #architecture #operating system
Architectural Support for Single Address Space Operating Systems (EJK, JSC, SJE), pp. 175–186.
ASPLOS-1991-BradleeEH #scheduling
Integrating Register Allocation and Instruction Scheduling for RISCs (DGB, SJE, RRH), pp. 122–131.
PLDI-1991-BradleeHE #scheduling
The Marion System for Retargetable Instruction Scheduling (DGB, RRH, SJE), pp. 229–240.
ASPLOS-1989-EggersK #parallel #performance #source code
The Effect of Sharing on the Cache and Bus Performance of Parallel Programs (SJE, RHK), pp. 257–270.
VLDB-1981-EggersOS #scalability #statistics
A Compression Technique for Large Statistical Data-Bases (SJE, FO, AS), pp. 424–434.
VLDB-1980-EggersS #performance
Efficient Access of Compressed Data (SJE, AS), pp. 205–211.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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