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Travelled to:
1 × USA
3 × Germany
5 × France
Collaborated with:
A.Jantsch S.Penolazzi A.Hemani J.Zhu K.Rosvall S.H.A.Niaki B.Navas J.Öberg Z.Lu T.Raudvere A.K.Singh E.Paone F.Robino G.Palermo V.Zaccaria C.Silvano
Talks about:
applic (5) design (4) time (4) system (3) real (3) reconfigur (2) constraint (2) transform (2) heterogen (2) platform (2)

Person: Ingo Sander

DBLP DBLP: Sander:Ingo

Contributed to:

DATE 20152015
DATE 20142014
DATE 20132013
DATE 20112011
DATE 20102010
DATE 20092009
DATE v1 20042004
DATE 20032003
DAC 20022002

Wrote 11 papers:

DATE-2015-PaoneRPZSS #constraints #framework #performance #platform
Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints (EP, FR, GP, VZ, IS, CS), pp. 736–741.
DATE-2014-RosvallS #constraints #design #framework #realtime
A constraint-based design space exploration framework for real-time applications on MPSoCs (KR, IS), pp. 1–6.
DATE-2013-NavasSO #array #configuration management #flexibility #framework #platform #reuse
The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks (BN, IS, JÖ), pp. 833–838.
DATE-2013-NiakiS #automation #embedded #parallel #simulation
An automated parallel simulation flow for heterogeneous embedded systems (SHAN, IS), pp. 27–30.
DATE-2011-PenolazziSH #energy #multi #performance #predict
Predicting bus contention effects on energy and performance in multi-processor SoCs (SP, IS, AH), pp. 1196–1199.
DATE-2010-PenolazziSH #energy #operating system #performance #predict #realtime
Predicting energy and performance overhead of Real-Time Operating Systems (SP, IS, AH), pp. 15–20.
DATE-2010-ZhuSJ #configuration management #cpu #design #performance #streaming
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs (JZ, IS, AJ), pp. 1035–1040.
DATE-2009-ZhuSJ #architecture #cpu #hybrid #realtime #scheduling #streaming
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures (JZ, IS, AJ), pp. 1506–1511.
DATE-v1-2004-RaudvereSSJ #abstraction #polynomial #verification
Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits (TR, AKS, IS, AJ), pp. 690–691.
DATE-2003-SanderJL #design #development
Development and Application of Design Transformations in ForSyDe (IS, AJ, ZL), pp. 10364–10369.
DAC-2002-SanderJ #communication #design #refinement
Transformation based communication and clock domain refinement for system design (IS, AJ), pp. 281–286.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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