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Used together with:
stt (12)
cach (5)
architectur (4)
effici (3)
memori (3)

Stem mram$ (all stems)

17 papers:

DACDAC-2015-WangJZWY #energy #performance
Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM (RW, LJ, YZ, LW, JY), p. 6.
DATEDATE-2015-KomalanTPFC
System level exploration of a STT-MRAM based level 1 data-cache (MPK, CT, JIGP, FTF, FC), pp. 1311–1316.
DATEDATE-2015-PajouhiFR #architecture #co-evolution #design #reliability
Device/circuit/architecture co-design of reliable STT-MRAM (ZP, XF, KR), pp. 1437–1442.
DATEDATE-2015-VatajeluNIP
STT MRAM-Based PUFs (EIV, GDN, MI, PP), pp. 872–875.
DATEDATE-2015-VatajeluRIRPF #estimation #metric #robust
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell (EIV, RRM, MI, MR, PP, JF), pp. 447–452.
DATEDATE-2014-BelKKS #fault #multi
Improving STT-MRAM density through multibit error correction (BDB, JK, CHK, SSS), pp. 1–6.
DATEDATE-2014-BishnoiEOT #power management #symmetry #termination
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM (RB, ME, FO, MBT), pp. 1–6.
DATEDATE-2013-NoguchiNAFAKNMN #energy #hybrid #memory management #performance
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory (HN, KN, KA, SF, EA, KK, TN, SM, HN), pp. 1813–1818.
DACDAC-2012-JiangZZY #embedded #multi #performance #scalability
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors (LJ, BZ, YZ, JY), pp. 907–912.
DACDAC-2012-ParkGMRR #architecture #design #energy #performance #using
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture (SPP, SKG, NNM, AR, KR), pp. 492–497.
DATEDATE-2012-AzevedoVBDGTPAM #architecture #fault
Impact of resistive-open defects on the heat current of TAS-MRAM architectures (JA, AV, AB, LD, PG, ATS, GP, JAH, KM), pp. 532–537.
DATEDATE-2012-GuptaPMR #optimisation
Layout-aware optimization of stt mrams (SKG, SPP, NNM, KR), pp. 1455–1458.
DACDAC-2010-WangCW #identification #performance
Fast identification of operating current for toggle MRAM by spiral search (SHW, CYC, CWW), pp. 923–928.
DACDAC-2009-XuCWZ
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing (WX, YC, XW, TZ), pp. 87–90.
HPCAHPCA-2009-SunDXLC #3d #architecture #novel
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (GS, XD, YX, JL, YC), pp. 239–249.
DACDAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.
DACDAC-2008-LiASR #array #design #memory management #modelling #probability #random #statistics
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement (JL, CA, SSS, KR), pp. 278–283.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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