Travelled to:1 × France
1 × USA
Collaborated with:Y.Leblebici P.Ienne T.Zhang G.Beanato P.Athanasopoulos A.K.Coskun F.Regazzoni M.Schwander S.Badel N.E.Evmorfopoulos C.Antoniadis A.Burg G.I.Stamoulis
Talks about:power (2) architectur (1) methodolog (1) standard (1) resourc (1) modular (1) librari (1) current (1) theori (1) resist (1)
Person: Alessandro Cevrero
DBLP: Cevrero:Alessandro
Contributed to:
2013
2011Wrote 3 papers:
- DATE-2013-CevreroEAILBS #estimation #performance
- Fast and accurate BER estimation methodology for I/O links based on extreme value theory (AC, NEE, CA, PI, YL, AB, GIS), pp. 503–508.
- DATE-2013-ZhangCBACL #3d #architecture #composition #manycore #named #performance
- 3D-MMC: a modular 3D multi-core architecture with efficient resource pooling (TZ, AC, GB, PA, AKC, YL), pp. 1241–1246.
- DAC-2011-CevreroRSBIL #library #logic #power management #standard
- Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library (AC, FR, MS, SB, PI, YL), pp. 1014–1019.