BibSLEIGH — Yusuf

Travelled to:

3 × Germany
4 × France
5 × USA

Collaborated with:

G.D.Micheli A.Tajalli M.H.B.Jamaa D.Atienza M.D.Marchi S.Bobba A.Cevrero P.Gaillardon D.Sacchetto F.K.Gürkaynak A.K.Coskun B.K.Boroujeni C.Piguet P.Ienne S.Badel L.G.Amarù C.Guiducci A.Schmid P.Muller S.M.Atarodi J.L.Ayala T.S.Rosing T.Zhang G.Beanato P.Athanasopoulos F.Regazzoni M.Schwander N.E.Evmorfopoulos C.Antoniadis A.Burg G.I.Stamoulis E.Guleyupoglu O.Inac A.P.Martinez P.Vietti X.Tang J.Sandrini M.Thammasack S.R.Omam M.M.Sabry A.Sridhar Y.Temiz S.Szczukiewicz N.Borhani J.R.Thome T.Brunschwiler B.Michel

Talks about:

power (6) circuit (5) nanowir (4) design (4) gate (4) architectur (3) multi (3) base (3) low (3) transistor (2)

Person: Yusuf Leblebici

DBLP: Leblebici:Yusuf

Contributed to:

2015

2013

2012

2011

2010

2009

2008

2005

Wrote 16 papers:

DATE-2015-GaillardonTSTOS #power management: A ultra-low-power FPGA based on monolithically integrated RRAMs (PEG, XT, JS, MT, SRO, DS, YL, GDM), pp. 1203–1208.
DAC-2013-GaillardonMABSLM #towards #using: Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
DATE-2013-CevreroEAILBS #estimation #performance: Fast and accurate BER estimation methodology for I/O links based on extreme value theory (AC, NEE, CA, PI, YL, AB, GIS), pp. 503–508.
DATE-2013-GaillardonABMSLM: Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
DATE-2013-ZhangCBACL #3d #architecture #composition #manycore #named #performance: 3D-MMC: a modular 3D multi-core architecture with efficient resource pooling (TZ, AC, GB, PA, AKC, YL), pp. 1241–1246.
DAC-2012-BobbaMLM #physics #synthesis: Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.
DAC-2011-CevreroRSBIL #library #logic #power management #standard: Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library (AC, FR, MS, SB, PI, YL), pp. 1014–1019.
DATE-2011-SabrySATLSBTBM #3d #design #towards: Towards thermally-aware design of 3D MPSoCs with inter-tier cooling (MMS, AS, DA, YT, YL, SS, NB, JRT, TB, BM), pp. 1466–1471.
DATE-2010-Kheradmand-BoroujeniPL #independence #novel #process: AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics (BKB, CP, YL), pp. 339–344.
DATE-2010-TajalliL #design #framework #power management #using: Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits (AT, YL), pp. 711–716.
DAC-2009-JamaaLM #array #multi: Decoding nanowire arrays fabricated with the multi-spacer patterning technique (MHBJ, YL, GDM), pp. 77–82.
DATE-2009-CoskunAARL #3d #architecture #manycore: Dynamic thermal management in 3D multicore architectures (AKC, JLA, DA, TSR, YL), pp. 1410–1415.
DAC-2008-JamaaALM #logic #programmable: Programmable logic circuits based on ambipolar CNFET (MHBJ, DA, YL, GDM), pp. 339–340.
DATE-2008-BadelGIMVGL #design #difference #standard: A Generic Standard Cell Design Methodology for Differential Circuit Styles (SB, EG, OI, APM, PV, FKG, YL), pp. 843–848.
DATE-2008-GuiducciSGL #architecture #interface #novel: Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces (CG, AS, FKG, YL), pp. 1328–1333.
DATE-2005-MullerTAL #design #multi #power management #top-down: Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit (PM, AT, SMA, YL), pp. 258–263.