BibSLEIGH — Paolo

Travelled to:

5 × France
5 × Germany
8 × USA

Collaborated with:

A.K.Verma P.Brisk L.Pozzi D.Novo M.Vuletic X.Jimenez P.Biswas H.Parandeh-Afshar F.Regazzoni K.Atasu A.Grießing N.D.Dutt A.G.Bayrak A.Becker S.E.Alaoui A.Cevrero Y.Leblebici T.Kluter E.Charbon L.Righetti N.Farahpour U.Ahmad F.Catthoor M.Stojilovic L.Saranovac F.Standaert J.Großschädl S.Tillich S.Banerjee N.Velickovic M.Schwander S.Badel V.Choudhary N.Dutt N.E.Evmorfopoulos C.Antoniadis A.Burg G.I.Stamoulis J.Deng Y.Fang Z.Du Y.Wang H.Li O.Temam X.Li Y.Chen C.Wu

Talks about:

automat (7) instruct (6) set (6) circuit (5) extens (5) arithmet (4) applic (4) base (4) specif (3) improv (3)

Person: Paolo Ienne

DBLP: Ienne:Paolo

Contributed to:

2015

2014

2013

2012

2011

2009

2008

2007

2006

2005

2004

2003

2002

1998

Wrote 27 papers:

DATE-2015-DengFDWLTINLCW #fault #hardware #network: Retraining-based timing error mitigation for hardware neural networks (JD, YF, ZD, YW, HL, OT, PI, DN, XL, YC, CW), pp. 593–596.
DATE-2014-BeckerNI #named #sketching: SKETCHILOG: Sketching combinational circuits (AB, DN, PI), pp. 1–4.
DATE-2014-NovoFIAC #approximate #case study #energy #performance #runtime: Energy efficient MIMO processing: A case study of opportunistic run-time approximations (DN, NF, PI, UA, FC), pp. 1–6.
DATE-2013-BayrakVRNBI: An EDA-friendly protection scheme against side-channel attacks (AGB, NV, FR, DN, PB, PI), pp. 410–415.
DATE-2013-CevreroEAILBS #estimation #performance: Fast and accurate BER estimation methodology for I/O links based on extreme value theory (AC, NEE, CA, PI, YL, AB, GIS), pp. 503–508.
DATE-2013-JimenezNI #named: Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime (XJ, DN, PI), pp. 226–229.
DATE-2013-NovoAI #estimation #fault #fixpoint #invariant #linear #trade-off: Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems (DN, SEA, PI), pp. 15–20.
DAC-2012-JimenezNI: Software controlled cell bit-density to improve NAND flash lifetime (XJ, DN, PI), pp. 229–234.
DATE-2012-StojilovicNSBI #flexibility: Selective flexibility: Breaking the rigidity of datapath merging (MS, DN, LS, PB, PI), pp. 1543–1548.
DAC-2011-BayrakRBSI #analysis #automation #towards: A first step towards automatic application of power analysis countermeasures (AGB, FR, PB, FXS, PI), pp. 230–235.
DAC-2011-CevreroRSBIL #library #logic #power management #standard: Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library (AC, FR, MS, SB, PI, YL), pp. 1014–1019.
DAC-2009-KluterBIC #automation #set: Way Stealing: cache-assisted automatic instruction set extensions (TK, PB, PI, EC), pp. 31–36.
DATE-2008-Parandeh-AfsharBI #integer #linear #programming #synthesis: Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming (HPA, PB, PI), pp. 1256–1261.
DATE-2008-VermaBI #design #latency #paradigm: Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design (AKV, PB, PI), pp. 1250–1255.
DAC-2007-BriskVIP #performance: Enhancing FPGA Performance for Arithmetic Circuits (PB, AKV, PI, HPA), pp. 334–337.
DAC-2007-VermaBI #composition #heuristic: Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits (AKV, PB, PI), pp. 404–409.
DATE-2007-VermaI #automation #scalability #synthesis: Automatic synthesis of compressor trees: reevaluating large counters (AKV, PI), pp. 443–448.
DAC-2006-VermaI #architecture #automation #towards: Towards the automatic exploration of arithmetic-circuit architectures (AKV, PI), pp. 445–450.
DATE-2006-BiswasDIP #architecture #automation #functional #identification: Automatic identification of application-specific functional units with architecturally visible storage (PB, NDD, PI, LP), pp. 212–217.
DATE-2006-GrossschadlIPTV #algorithm #case study #design #encryption #set: Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography (JG, PI, LP, ST, AKV), pp. 218–223.
DATE-2005-BiswasBDPI #generative #named #set: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement (PB, SB, NDD, LP, PI), pp. 1246–1251.
DAC-2004-BiswasCAPID #memory management #set: Introduction of local memory elements in instruction set extensions (PB, VC, KA, LP, PI, ND), pp. 729–734.
DAC-2004-VuleticPI #configuration management #memory management: Virtual memory window for application-specific reconfigurable coprocessors (MV, LP, PI), pp. 948–953.
DATE-v1-2004-VuleticRPI #configuration management #interface #operating system: Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors (MV, LR, LP, PI), p. 748.
DAC-2003-AtasuPI #architecture #automation #constraints: Automatic application-specific instruction-set extensions under microarchitectural constraints (KA, LP, PI), pp. 256–261.
DATE-2002-PozziVI #automation #embedded #identification: Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors (LP, MV, PI), p. 1138.
DAC-1998-IenneG #case study #design #experience #question #standard #tool support: Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? (PI, AG), pp. 396–401.