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Travelled to:
1 × France
1 × USA
Collaborated with:
D.Goren M.Zelikson R.Gordin I.A.Wagner B.Livshitz A.Sherman T.C.Galambos A.Barger Y.Tretiakov R.A.Groves J.Park D.L.Jordan S.E.Strang R.Singh C.E.Dickey D.L.Harame
Talks about:
interconnect (2) methodolog (2) transmiss (2) bandwidth (2) design (2) line (2) high (2) chip (2) base (2) awar (2)

Person: Alon Amir

DBLP DBLP: Amir:Alon

Contributed to:

DAC 20032003
DATE 20022002

Wrote 2 papers:

DAC-2003-GorenZGWBALSTGPJSSDH #design #modelling
On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices (DG, MZ, RG, IAW, AB, AA, BL, AS, YT, RAG, JP, DLJ, SES, RS, CED, DLH), pp. 724–727.
DATE-2002-GorenZGGLASW #approach #design
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach (DG, MZ, TCG, RG, BL, AA, AS, IAW), pp. 804–811.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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