Travelled to:1 × Brazil
1 × Germany
2 × USA
Collaborated with:Y.Kwon S.Kim B.Cheon E.Lee L.Wang X.Wen P.Hsu J.Cho H.Chao S.Wu D.Goren M.Zelikson R.Gordin I.A.Wagner A.Barger A.Amir B.Livshitz A.Sherman Y.Tretiakov R.A.Groves D.L.Jordan S.E.Strang R.Singh C.E.Dickey D.L.Harame S.D.Posluszny N.Aoki D.Boerstler P.K.Coulman S.H.Dhong B.K.Flachs H.P.Hofstee N.Kojima O.Kwon K.Lee D.Meltzer K.J.Nowka J.Peter J.Silberman O.Takahashi P.Villarrubia
Talks about:design (3) methodolog (2) content (2) high (2) microprocessor (1) interconnect (1) architectur (1) transmiss (1) implement (1) bandwidth (1)
Person: J. Park
DBLP: Park:J=
Contributed to:
2007
2005
20032000Wrote 5 papers:
- ICDAR-2007-KimPK #architecture #embedded
- An Embedded OCR Software Architecture for Enhancing Portability (SK, JP, YBK), pp. 1004–1008.
- ICDAR-2007-KwonP #analysis #implementation #recognition
- Implementation of Content Analysis System for Recognition of Journals_ Table of Contents (YBK, JP), pp. 1018–1022.
- DATE-2005-CheonLWWHCPCW #logic
- At-Speed Logic BIST for IP Cores (BC, EL, LTW, XW, PH, JC, JP, HC, SW), pp. 860–861.
- DAC-2003-GorenZGWBALSTGPJSSDH #design #modelling
- On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices (DG, MZ, RG, IAW, AB, AA, BL, AS, YT, RAG, JP, DLJ, SES, RS, CED, DLH), pp. 724–727.
- DAC-2000-PoslusznyABCDFHKKLMNPPSTV #design
- “Timing closure by design”, a high frequency microprocessor design methodology (SDP, NA, DB, PKC, SHD, BKF, HPH, NK, OK, KL, DM, KJN, JP, JP, JS, OT, PV), pp. 712–717.