Travelled to:1 × Germany
2 × France
2 × USA
Collaborated with:D.Gajski P.Razaghi D.Lee L.K.John K.He M.Orshansky L.Cai H.Yu O.Bringmann W.Ecker A.Goyal D.Müller-Gritschneder P.Sasidharan S.Singh J.Peng D.Shin A.Nakamura D.Araki Y.Nishihara
Talks about:system (3) design (3) simul (3) explor (2) level (2) accur (2) time (2) rtos (2) fast (2) implement (1)
Person: Andreas Gerstlauer
DBLP: Gerstlauer:Andreas
Contributed to:
20152011
200820042003Wrote 7 papers:
- DATE-2015-BringmannEGGMSS #generative #prototype #simulation
- The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems (OB, WE, AG, AG, DMG, PS, SS), pp. 1698–1707.
- DATE-2015-LeeJG #functional #hardware #performance #simulation
- Dynamic power and performance back-annotation for fast and accurate functional hardware simulation (DL, LKJ, AG), pp. 1126–1131.
- DATE-2011-HeGO #design #energy
- Controlled timing-error acceptance for low energy IDCT design (KH, AG, MO), pp. 758–763.
- DATE-2011-RazaghiG #development #embedded #manycore #realtime
- Host-compiled multicore RTOS simulator for embedded real-time software development (PR, AG), pp. 222–227.
- DAC-2008-GerstlauerPSGNAN #implementation #specification
- Specify-explore-refine (SER): from specification to implementation (AG, JP, DS, DG, AN, DA, YN), pp. 586–591.
- DAC-2004-CaiGG #agile #design #profiling
- Retargetable profiling for rapid, early system-level design space exploration (LC, AG, DG), pp. 281–286.
- DATE-2003-GerstlauerYG #design #modelling
- RTOS Modeling for System Level Design (AG, HY, DG), pp. 10130–10135.