BibSLEIGH — Daniel_Mueller-Gritschneder

Travelled to:

2 × France
2 × Germany
2 × USA

Collaborated with:

U.Schlichtmann K.Lu V.Todorov H.Reinig H.Gräb M.Jassi E.Wallander M.Greim O.Bringmann W.Ecker A.Gerstlauer A.Goyal P.Sasidharan S.Singh J.Oetjens N.Bannow M.Becker A.Burger M.Chaari S.Chakraborty R.Drechsler K.Grüttner T.Kruse C.Kuznik H.M.Le M.Mauderer W.Müller F.Poppen H.Post S.Reiter W.Rosenstiel S.Roth A.v.Schwerin B.Tabacaru A.Viehl

Talks about:

prototyp (4) virtual (4) simul (3) level (3) time (3) transact (2) system (2) specif (2) integr (2) model (2)

Person: Daniel Müller-Gritschneder

DBLP: M=uuml=ller-Gritschneder:Daniel

Contributed to:

2015

2014

2013

2012

2010

Wrote 10 papers:

DAC-2015-JassiMS #design #grammarware #integration #named: GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs (MJ, DMG, US), p. 6.
DATE-2015-BringmannEGGMSS #generative #prototype #simulation: The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems (OB, WE, AG, AG, DMG, PS, SS), pp. 1698–1707.
DAC-2014-OetjensBBBBCCDEGKKLM0MPPRRRSSTV #challenge #evaluation #prototype #research #safety #state of the art #using: Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges (JHO, NB, MB, OB, AB, MC, SC, RD, WE, KG, TK, CK, HML, MM, WM, DMG, FP, HP, SR, WR, SR, US, AvS, BAT, AV), p. 6.
DATE-2013-LuMS #embedded #performance #simulation: Fast cache simulation for host-compiled simulation of embedded software (KL, DMG, US), pp. 637–642.
DATE-2013-LuMS13a #estimation: Analytical timing estimation for temporally decoupled TLMs considering resource conflicts (KL, DMG, US), pp. 1161–1166.
DATE-2013-Mueller-GritschnederLWGS #case study #framework #platform #prototype #realtime: A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot (DMG, KL, EW, MG, US), pp. 1331–1334.
DATE-2013-TodorovMRS #approach #clustering #synthesis: A spectral clustering approach to application-specific network-on-chip synthesis (VT, DMG, HR, US), pp. 1783–1788.
DATE-2012-LuMS #abstraction #modelling #prototype #transaction: Accurately timed transaction level models for virtual prototyping at high abstraction level (KL, DMG, US), pp. 135–140.
DATE-2012-TodorovMRS #approximate #automation #memory management #transaction: Automated construction of a cycle-approximate transaction level model of a memory controller (VT, DMG, HR, US), pp. 1066–1071.
DATE-2010-Mueller-GritschnederG #specification: Computation of yield-optimized Pareto fronts for analog integrated circuit specifications (DMG, HG), pp. 1088–1093.