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Travelled to:
2 × France
4 × Germany
4 × USA
Collaborated with:
M.Velten M.Bauer A.Goyal V.Esen T.Steininger L.Zafari R.Henftling A.Zinn M.Zambaldi M.Hull M.Chaari B.Tabacaru T.Kruse C.Novello R.Schwencker O.Bringmann D.Müller-Gritschneder L.Schönberg A.Gerstlauer P.Sasidharan S.Singh W.Kruijtzer P.v.d.Wolf E.A.d.Kock J.Stuyt A.Mayer S.Hustin C.Amerijckx S.d.Paoli E.Vaumorin J.Oetjens N.Bannow M.Becker A.Burger S.Chakraborty R.Drechsler K.Grüttner C.Kuznik H.M.Le M.Mauderer W.Müller F.Poppen H.Post S.Reiter W.Rosenstiel S.Roth U.Schlichtmann A.v.Schwerin A.Viehl
Talks about:
system (5) simul (4) base (4) approach (3) testbench (2) prototyp (2) interact (2) virtual (2) present (2) generat (2)

Person: Wolfgang Ecker

DBLP DBLP: Ecker:Wolfgang

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DATE 20102010
DATE 20082008
DATE 20072007
DAC 20032003
DATE 20032003
DAC 19971997

Wrote 12 papers:

DAC-2015-ChaariENTK #approach #modelling #safety
A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems (MC, WE, CN, BAT, TK), p. 6.
DATE-2015-BringmannEGGMSS #generative #prototype #simulation
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems (OB, WE, AG, AG, DMG, PS, SS), pp. 1698–1707.
DAC-2014-EckerVZG #design
Metasynthesis for Designing Automotive SoCs (WE, MV, LZ, AG), p. 6.
DAC-2014-OetjensBBBBCCDEGKKLM0MPPRRRSSTV #challenge #evaluation #prototype #research #safety #state of the art #using
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges (JHO, NB, MB, OB, AB, MC, SC, RD, WE, KG, TK, CK, HML, MM, WM, DMG, FP, HP, SR, WR, SR, US, AvS, BAT, AV), p. 6.
DATE-2014-EckerVZG #approach #metamodelling #synthesis
The metamodeling approach to system level synthesis (WE, MV, LZ, AG), pp. 1–2.
DATE-2010-EckerESSV #embedded #modelling
TLM+ modeling of embedded HW/SW systems (WE, VE, RS, TS, MV), pp. 75–80.
DATE-2008-KruijtzerWKSEMHAPV #industrial #integration #standard
Industrial IP Integration Flows based on IP-XACT Standards (WK, PvdW, EAdK, JS, WE, AM, SH, CA, SdP, EV), pp. 32–37.
DATE-2007-EckerESSVH #abstraction #interactive #performance #representation #simulation
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance (WE, VE, LS, TS, MV, MH), pp. 767–772.
DATE-2007-EckerESVH #framework #implementation #interactive #transaction
Interactive presentation: Implementation of a transaction level assertion framework in SystemC (WE, VE, TS, MV, MH), pp. 894–899.
DAC-2003-HenftlingZBZE #architecture
Re-use-centric architecture for a fully accelerated testbench environment (RH, AZ, MB, MZ, WE), pp. 372–375.
DATE-2003-HenftlingZBEZ #generative #platform
Platform-Based Testbench Generation (RH, AZ, MB, WE, MZ), pp. 11038–11045.
DAC-1997-BauerE #approach #hardware
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach (MB, WE), pp. 774–779.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.