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Travelled to:
1 × France
2 × Germany
Collaborated with:
A.Makosiej A.Vladimirescu A.Amara F.Clermidy N.Jovanovic S.Onkaraiah H.Oucheikh O.Turkyilmaz E.Vianello J.M.Portal M.Bocquet E.Beigné A.Valentian B.Giraud T.Benoist Y.Thonnart S.Bernard G.Moritz O.Billoint Y.Maneglia P.Flatresse J.Noël F.Abouzeid B.Pelloux-Prayer A.Grover S.Clerc P.Roche J.L.Coz S.Engels R.Wilson
Talks about:
design (2) ultra (2) silicon (1) voltag (1) stabil (1) resist (1) orient (1) memori (1) deplet (1) applic (1)

Person: Olivier Thomas

DBLP DBLP: Thomas:Olivier

Contributed to:

DATE 20142014
DATE 20132013
DATE 20122012

Wrote 3 papers:

DATE-2014-ClermidyJOOTTVPB #question
Resistive memories: Which applications? (FC, NJ, SO, HO, OT, OT, EV, JMP, MB), pp. 1–6.
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.
DATE-2012-MakosiejTVA #design #embedded #optimisation #power management
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization (AM, OT, AV, AA), pp. 93–98.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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