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Travelled to:
7 × USA
Collaborated with:
K.J.Kerns I.L.Wemple S.M.Kang J.T.Yao R.R.Daniels D.G.Saab I.N.Hajj Y.Liu C.H.Chan J.P.Harrang
Talks about:
circuit (4) model (4) simul (3) transform (2) congruenc (2) network (2) analysi (2) reduct (2) effici (2) macromodel (1)

Person: Andrew T. Yang

DBLP DBLP: Yang:Andrew_T=

Contributed to:

DAC 19971997
DAC 19961996
DAC 19951995
DAC 19931993
DAC 19911991
DAC 19891989
DAC 19881988

Wrote 7 papers:

DAC-1997-KernsY #congruence #network #reduction
Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations (KJK, ATY), pp. 34–39.
DAC-1996-KernsY #analysis #congruence #multi #network #performance #reduction #scalability
Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via Congruence Transformations (KJK, ATY), pp. 280–285.
DAC-1995-WempleY #analysis #megamodelling #using
Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels (ILW, ATY), pp. 439–444.
DAC-1993-YangLYD #performance #simulation
An Efficient Non-Quasi-Static Diode Model for Circuit Simulation (ATY, YL, JTY, RRD), pp. 720–725.
DAC-1991-YangCYDH #modelling #parametricity #simulation
Modeling and Simulation of High-Frequency Integrated Circuits Based on Scattering Parameters (ATY, CHC, JTY, RRD, JPH), pp. 752–757.
DAC-1989-YangK #development #named #novel #simulation
iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development (ATY, SMK), pp. 630–633.
DAC-1988-SaabYH #modelling
Delay Modeling and Time of Bipolar Digital Circuits (DGS, ATY, INH), pp. 288–293.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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