Travelled to:2 × USA
Collaborated with:H.M.Jacobson P.Bose Z.Hu A.Buyuktosunoglu V.V.Zyuban R.J.Eickemeyer L.Eisen J.Griswell D.Logan J.M.Tendler J.G.Clabes J.Friedrich M.Sweet J.DiLullo S.G.Chu D.W.Plass J.Dawson P.Muench L.Powell M.S.Floyd M.Lee M.Goulet J.Wagoner N.S.Schwartz S.L.Runyon G.Gorman P.Restle R.N.Kalla J.McGill J.S.Dodson
Talks about:microprocessor (1) processor (1) implement (1) stretch (1) server (1) effici (1) design (1) power (1) limit (1) clock (1)
Person: Balaram Sinharoy
DBLP: Sinharoy:Balaram
Contributed to:
2005
2004Wrote 2 papers:
- HPCA-2005-JacobsonBHBZEEGLST #performance
- Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors (HMJ, PB, ZH, AB, VVZ, RJE, LE, JG, DL, BS, JMT), pp. 238–242.
- DAC-2004-ClabesFSDCPDMPFSLGWSRGRKMD #design #implementation
- Design and implementation of the POWER5 microprocessor (JGC, JF, MS, JD, SGC, DWP, JD, PM, LP, MSF, BS, ML, MG, JW, NSS, SLR, GG, PR, RNK, JM, JSD), pp. 670–672.