BibSLEIGH — Proceedings of the 11th International Conference on High-Performance Computer Architecture

Proceedings of the 11th International Conference on High-Performance Computer Architecture
HPCA, 2005.

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@proceedings{HPCA-2005,
	address       = "San Francisco, California, USA",
	ee            = "http://www.computer.org/csdl/proceedings/hpca/2005/2275/00/index.html",
	isbn          = "0-7695-2275-0",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the 11th International Conference on High-Performance Computer Architecture}",
	year          = 2005,
}

Contents (35 items)

HPCA-2005-Weber #roadmap: Trends in High-Performance Processors (FW), p. 3.
HPCA-2005-TuckT #parallel #predict #thread: Multithreaded Value Prediction (NT, DMT), pp. 5–15.
HPCA-2005-KirmanKCM: Checkpointed Early Load Retirement (NK, MK, MC, JFM), pp. 16–27.
HPCA-2005-BalasubramonianMRV #architecture #performance: Microarchitectural Wire Management for Performance and Power in Partitioned Architectures (RB, NM, KR, VV), pp. 28–39.
HPCA-2005-KondoN #clustering #performance #power management: A Small, Fast and Low-Power Register File by Bit-Partitioning (MK, HN), pp. 40–49.
HPCA-2005-SundaresanM #energy #modelling: Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses (KS, NRM), pp. 51–60.
HPCA-2005-ChaparroMGG #reduction: Distributing the Frontend for Temperature Reduction (PC, GM, JG, AG), pp. 61–70.
HPCA-2005-LiBHS #architecture #energy #performance #smt: Performance, Energy, and Thermal Considerations for SMT and CMP Architectures (YL, DMB, ZH, KS), pp. 71–82.
HPCA-2005-VenkatesanAR #memory management #power management: Tapping ZettaRAMTM for Low-Power Memory Systems (RKV, ASAZ, ER), pp. 83–94.
HPCA-2005-WillmannKRP #interface #network #performance #programmable: An Efficient Programmable 10 Gigabit Ethernet Network Interface Card (PW, HyK, SR, VSP), pp. 96–107.
HPCA-2005-DuatoJFNGF #effectiveness #multi #network #scalability: A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks (JD, IJ, JF, FN, PJG, TNF), pp. 108–119.
HPCA-2005-ChenPWHP #design #power management: Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems (XC, LSP, GYW, YKH, PRP), pp. 120–131.
HPCA-2005-AhnED #architecture #parallel: Scatter-Add in Data Parallel Architectures (JHA, ME, WJD), pp. 132–142.
HPCA-2005-JonesOAG #queue #reduction: Software Directed Issue Queue Power Reduction (TMJ, MFPO, JA, AG), pp. 144–153.
HPCA-2005-MengSK #on the #power management #reduction: On the Limits of Leakage Power Reduction in Caches (YM, TS, RK), pp. 154–165.
HPCA-2005-HasanJVB #smt: Heat Stroke: Power-Density-Based Denial of Service in SMT (JH, AJ, TNV, CEB), pp. 166–177.
HPCA-2005-WuJMC #adaptation #multi: Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors (QW, PJ, MM, DWC), pp. 178–189.
HPCA-2005-JaleelJ #memory management #using: Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions (AJ, BLJ), pp. 191–200.
HPCA-2005-HallnorR #memory management: A Unified Compressed Memory Hierarchy (EGH, SKR), pp. 201–212.
HPCA-2005-ZhuZ #comparison #memory management #optimisation #performance #smt: A Performance Comparison of DRAM Memory System Optimizations for SMT Processors (ZZ, ZZ), pp. 213–224.
HPCA-2005-SpracklenCA #effectiveness #multi: Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications (LS, YC, SGA), pp. 225–236.
HPCA-2005-JacobsonBHBZEEGLST #performance: Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors (HMJ, PB, ZH, AB, VVZ, RJE, LE, JG, DL, BS, JMT), pp. 238–242.
HPCA-2005-MukherjeeER #architecture #fault #perspective #problem: The Soft Error Problem: An Architectural Perspective (SSM, JSE, SKR), pp. 243–247.
HPCA-2005-SpracklenA #challenge #multi #thread: Chip Multithreading: Opportunities and Challenges (LS, SGA), pp. 248–252.
HPCA-2005-RanganathanJ #architecture #enterprise #research #roadmap: Enterprise IT Trends and Implications for Architecture Research (PR, NPJ), pp. 253–256.
HPCA-2005-Hofstee #architecture #performance: Power Efficient Processor Architecture and The Cell Processor (HPH), pp. 258–262.
HPCA-2005-HwuP #architecture #future of #industrial #perspective #research: The Future of Computer Architecture Research: An Industrial Perspective (WmWH, SJP), p. 264.
HPCA-2005-YiKSLH #simulation: Characterizing and Comparing Prevailing Simulation Techniques (JJY, SVK, RS, DJL, DMH), pp. 266–277.
HPCA-2005-LauSC #classification #predict: Transition Phase Classification and Prediction (JL, SS, BC), pp. 278–289.
HPCA-2005-QinLZ #detection #memory management #named: SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs (FQ, SL, YZ), pp. 291–302.
HPCA-2005-CorlissLR #debugging #interactive: Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE (MLC, ECL, AR), pp. 303–314.
HPCA-2005-AnanianAKLL #bound #memory management #transaction: Unbounded Transactional Memory (CSA, KA, BCK, CEL, SL), pp. 316–327.
HPCA-2005-MartyBHHMW #multi #using: Improving Multiple-CMP Systems Using Token Coherence (MRM, JDB, MDH, AJH, MMKM, DAW), pp. 328–339.
HPCA-2005-ChandraGKS #architecture #multi #predict #thread: Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture (DC, FG, SK, YS), pp. 340–351.
HPCA-2005-ZhangGYZG #memory management #multi #named #security #symmetry: SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors (YZ, LG, JY, XZ, RG), pp. 352–362.

Proceedings of the 11th International Conference on High-Performance Computer ArchitectureHPCA, 2005.

Contents (35 items)

Proceedings of the 11th International Conference on High-Performance Computer Architecture
HPCA, 2005.