Travelled to:4 × USA
Collaborated with:S.W.Keckler V.Nagarajan B.Falsafi P.Gratz Rakesh Kumar 0003 J.Hestness O.Mutlu S.Novakovic A.Daglis E.Bugnion S.Fytraki E.Vlachos Y.O.Koçberber Antonios Katsarakis Vasilis Gavrielatos M. R. Siavash Katebzadeh Arpit Joshi A.Dragojevic
Talks about:chip (2) interconnect (1) bottleneck (1) protocol (1) programm (1) lineariz (1) instruct (1) topolog (1) shotgun (1) network (1)
Person: Boris Grot
DBLP: Grot:Boris
Contributed to:
2014
20142009200820182020Wrote 6 papers:
- ASPLOS-2014-NovakovicDBFG
- Scale-out NUMA (SN, AD, EB, BF, BG), pp. 3–18.
- HPCA-2014-FytrakiVKFG #monitoring #named #programmable
- FADE: A programmable filtering accelerator for instruction-grain monitoring (SF, EV, YOK, BF, BG), pp. 108–119.
- HPCA-2009-GrotHKM
- Express Cube Topologies for on-Chip Interconnects (BG, JH, SWK, OM), pp. 163–174.
- HPCA-2008-GratzGK
- Regional congestion awareness for load balance in networks-on-chip (PG, BG, SWK), pp. 203–214.
- ASPLOS-2018-0003GN
- Blasting through the Front-End Bottleneck with Shotgun (RK0, BG, VN), pp. 30–42.
- ASPLOS-2020-KatsarakisGKJDG #fault tolerance #named #performance #protocol #replication
- Hermes: A Fast, Fault-Tolerant and Linearizable Replication Protocol (AK, VG, MRSK, AJ, AD, BG, VN), pp. 201–217.