BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Canada
1 × Turkey
10 × USA
2 × China
Collaborated with:
D.Burger W.J.Dally B.Robatmili B.Grot P.Gratz N.Agarwal D.W.Nellans M.O'Connor M.S.S.Govindan C.Malachowsky C.Kim N.P.Carter K.S.McKinley J.Hestness O.Mutlu K.K.Agaram C.Lin R.Desikan S.Sethumadhavan J.R.Diamond A.Smith M.Stephenson T.F.Wenisch Y.Lee R.Krashinsky V.Grover K.Asanovic R.A.v.d.Geijn K.Goto D.Li H.Esmaeilzadeh A.Putnam M.Pellauer Yakun Sophia Shao J.Clemons N.C.Crago Kartik Hegde R.Venkatesan C.W.Fletcher J.S.Emer M.Gebhart B.A.Maher K.E.Coons M.Marino N.Ranganathan J.H.Burrill
Talks about:
architectur (3) system (3) data (3) chip (3) distribut (2) structur (2) perform (2) memori (2) gpus (2) cach (2)

Person: Stephen W. Keckler

DBLP DBLP: Keckler:Stephen_W=

Contributed to:

ASPLOS 20152015
HPCA 20152015
CGO 20132013
DAC 20132013
HPCA 20132013
HPCA 20112011
ASPLOS 20092009
HPCA 20092009
HPCA 20082008
PPoPP 20082008
ISMM 20062006
ASPLOS 20042004
ASPLOS 20022002
ASPLOS 19941994
ASPLOS 20192019

Wrote 15 papers:

ASPLOS-2015-AgarwalNSOK #memory management
Page Placement Strategies for GPUs within Heterogeneous Memory Systems (NA, DWN, MS, MO, SWK), pp. 607–618.
Unlocking bandwidth for GPUs in CC-NUMA systems (NA, DWN, MO, SWK, TFW), pp. 354–365.
CGO-2013-LeeKGKA #architecture #convergence
Convergence and scalarization for data-parallel architectures (YL, RK, VG, SWK, KA), p. 11.
DAC-2013-DallyMK #design #tool support
21st century digital design tools (WJD, CM, SWK), p. 6.
HPCA-2013-RobatmiliLEGSPBK #architecture #effectiveness #how #manycore #predict
How to implement effective prediction and forwarding for fusable dynamic multicore architectures (BR, DL, HE, MSSG, AS, AP, DB, SWK), pp. 460–471.
HPCA-2011-RobatmiliGBK #distributed
Exploiting criticality to reduce bottlenecks in distributed uniprocessors (BR, MSSG, DB, SWK), pp. 431–442.
ASPLOS-2009-GebhartMCDGMRRSBKBM #evaluation
An evaluation of the TRIPS computer system (MG, BAM, KEC, JRD, PG, MM, NR, BR, AS, JHB, SWK, DB, KSM), pp. 1–12.
Express Cube Topologies for on-Chip Interconnects (BG, JH, SWK, OM), pp. 163–174.
Regional congestion awareness for load balance in networks-on-chip (PG, BG, SWK), pp. 203–214.
PPoPP-2008-DiamondRKGGB #algebra #distributed #linear #performance
High performance dense linear algebra on a spatially distributed processor (JRD, BR, SWK, RAvdG, KG, DB), pp. 63–72.
ISMM-2006-AgaramKLM #data type #memory management #performance
Decomposing memory performance: data structures and phases (KKA, SWK, CL, KSM), pp. 95–103.
ASPLOS-2004-DesikanSBK #architecture #scalability
Scalable selective re-execution for EDGE architectures (RD, SS, DB, SWK), pp. 120–132.
ASPLOS-2002-KimBK #adaptation
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (CK, DB, SWK), pp. 211–222.
ASPLOS-1994-CarterKD #hardware #performance
Hardware Support for Fast Capability-based Addressing (NPC, SWK, WJD), pp. 319–327.
ASPLOS-2019-PellauerSCCHVKF #composition #distributed #named #performance
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration (MP, YSS, JC, NCC, KH, RV, SWK, CWF, JSE), pp. 137–151.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.