Travelled to:4 × USA
Collaborated with:S.W.Keckler B.Grot H.Jang J.Kim K.H.Yum E.J.Kim J.Won X.Chen J.Hu V.Soteriou M.Gebhart B.A.Maher K.E.Coons J.R.Diamond M.Marino N.Ranganathan B.Robatmili A.Smith J.H.Burrill D.Burger K.S.McKinley
Talks about:network (2) chip (2) interconnect (1) bootstrap (1) bandwidth (1) artifici (1) congest (1) system (1) region (1) neural (1)
Person: Paul Gratz
DBLP: Gratz:Paul
Contributed to:
2015
2014
20092008Wrote 4 papers:
- DAC-2015-JangKGY0 #design
- Bandwidth-efficient on-chip interconnect designs for GPGPUs (HJ, JK, PG, KHY, EJK), p. 6.
- HPCA-2014-WonCGHS #learning #network #online #power management
- Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management (JYW, XC, PG, JH, VS), pp. 308–319.
- ASPLOS-2009-GebhartMCDGMRRSBKBM #evaluation
- An evaluation of the TRIPS computer system (MG, BAM, KEC, JRD, PG, MM, NR, BR, AS, JHB, SWK, DB, KSM), pp. 1–12.
- HPCA-2008-GratzGK
- Regional congestion awareness for load balance in networks-on-chip (PG, BG, SWK), pp. 203–214.