Travelled to:2 × France
2 × Germany
Collaborated with:K.Chakrabarty D.K.Pradhan V.Iyengar Z.Link M.Gössel B.Yang A.Sanghani S.Sarangi
Talks about:test (5) scan (4) chip (4) base (4) identifi (2) diagnosi (2) schedul (2) network (2) system (2) fault (2)
Person: Chunsheng Liu
DBLP: Liu:Chunsheng
Contributed to:
2011200620032002Wrote 6 papers:
- DATE-2011-YangSSL #reduction #testing
- A clock-gating based capture power droop reduction methodology for at-speed scan testing (BY, AS, SS, CL), pp. 197–203.
- DATE-2006-LiuI #optimisation #scheduling #using
- Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking (CL, VI), pp. 652–657.
- DATE-2006-LiuLP #scheduling
- Reuse-based test access and integrated test scheduling for network-on-chip (CL, ZL, DKP), pp. 303–308.
- DATE-2003-LiuC #approach #fault #identification
- A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis (CL, KC), pp. 10230–10237.
- DATE-2003-PradhanLC #detection #fault #generative #named #novel
- EBIST: A Novel Test Generator with Built-In Fault Detection Capability (DKP, CL, KC), pp. 10224–10229.
- DATE-2002-LiuCG #identification
- An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment (CL, KC, MG), pp. 382–386.