Travelled to:1 × France
2 × Germany
3 × USA
Collaborated with:K.Chakrabarty E.J.Marinissen C.Liu G.Grise M.Taylor A.Sehgal M.D.Krasniewski A.Chandra S.Schweizer
Talks about:test (6) optim (4) tam (4) soc (4) use (3) wrapper (2) schedul (2) reduct (2) data (2) chip (2)
Person: Vikram Iyengar
DBLP: Iyengar:Vikram
Contributed to:
2006
20062003200320022002Wrote 6 papers:
- DAC-2006-IyengarGT #flexibility #scalability
- A flexible and scalable methodology for GHz-speed structural test (VI, GG, MT), pp. 314–319.
- DATE-2006-LiuI #optimisation #scheduling #using
- Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking (CL, VI), pp. 652–657.
- DAC-2003-SehgalIKC #multi #reduction #using
- Test cost reduction for SOCs using virtual TAMs and lagrange multipliers (AS, VI, MDK, KC), pp. 738–743.
- DATE-2003-IyengarCSC #approach #optimisation #testing #using
- A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization (VI, AC, SS, KC), pp. 11188–11190.
- DAC-2002-IyengarCM #constraints #reduction #scheduling
- Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs (VI, KC, EJM), pp. 685–690.
- DATE-2002-IyengarCM #performance #scalability
- Efficient Wrapper/TAM Co-Optimization for Large SOCs (VI, KC, EJM), pp. 491–498.