Travelled to:1 × Germany
3 × France
Collaborated with:J.M.Daga E.Ottaviano S.Turgis J.M.Portal A.Verle X.Michel N.Azémard P.Maurine W.Rahajandraibe C.Dufaza B.Cialdella B.Majoux V.Chowdhury
Talks about:low (3) voltag (2) applic (2) power (2) cmos (2) temperatur (1) structur (1) protocol (1) determin (1) paramet (1)
Person: Daniel Auvergne
DBLP: Auvergne:Daniel
Contributed to:
2005200219981997Wrote 4 papers:
- DATE-2005-VerleMAMA #optimisation #power management #protocol
- Low Power Oriented CMOS Circuit Optimization Protocol (AV, XM, NA, PM, DA), pp. 640–645.
- DATE-2002-RahajandraibeDACMC #parametricity
- Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications (WR, CD, DA, BC, BM, VC), pp. 316–321.
- DATE-1998-DagaOA
- Temperature Effect on Delay for Low Voltage Applications (JMD, EO, DA), pp. 680–685.
- EDTC-1997-TurgisDPA #modelling
- Internal power modelling and minimization in CMOS inverters (ST, JMD, JMP, DA), pp. 603–608.