Travelled to:1 × Germany
2 × France
2 × USA
Collaborated with:C.Forzan L.T.Pileggi A.J.Strojwas N.Andrikos L.Lavagno C.P.Sotiriou E.Charbon E.Malavasi A.L.Sangiovanni-Vincentelli P.J.Doriol Y.Villavicencio M.Rotigni G.Graziosi
Talks about:awar (2) microcontrol (1) desynchron (1) placement (1) synthesi (1) synchron (1) simultan (1) behavior (1) librari (1) congest (1)
Person: Davide Pandini
DBLP: Pandini:Davide
Contributed to:
2009
2007200520021994Wrote 5 papers:
- DATE-2009-DoriolVFRGP #design
- EMC-aware design on a microcontroller for automotive applications (PJD, YV, CF, MR, GG, DP), pp. 1208–1213.
- DAC-2007-AndrikosLPS
- A Fully-Automated Desynchronization Flow for Synchronous Circuits (NA, LL, DP, CPS), pp. 982–985.
- DATE-2005-ForzanP #analysis #behaviour #library #modelling
- Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis (CF, DP), pp. 982–983.
- DATE-2002-PandiniPS #logic #synthesis
- Congestion-Aware Logic Synthesis (DP, LTP, AJS), pp. 664–671.
- DAC-1994-CharbonMPS #optimisation
- Simultaneous Placement and Module Optimization of Analog IC’s (EC, EM, DP, ALSV), pp. 31–35.