BibSLEIGH — Luciano

Travelled to:

1 × Italy
11 × USA
5 × Germany
7 × France

Collaborated with:

A.L.Sangiovanni-Vincentelli C.Passerone A.Kondratyev Y.Watanabe J.Cortadella E.Sentovich M.Meyer M.Sgroi M.Kishinevsky A.Yakovlev A.L.Rosa H.Hsieh M.T.Lazarescu G.Cabodi P.Camurati S.Quer A.Jurecska C.P.Sotiriou F.Gregoretti L.M.Reyneri F.Balarin M.Lajolo M.Chiodo E.Tuncer C.Kim K.Keutzer P.Giusto N.Andrikos D.Pandini V.Shah L.Vanzago B.Bhattacharya J.Cambonie F.Cucinotta A.Serra A.Raghunathan S.Dey Y.Hong P.A.Beerel P.C.McGeer A.Saldanha C.W.Moon R.K.Brayton J.Brunel M.D.Natale A.Ferrari K.Lwin G.Arrigoni L.Duchini M.Rebaudengo M.S.Reorda M.Violante B.Tabbara E.Filippi F.Intini R.Passerone T.Cuatto A.Damiano C.Sansoè M.Massot S.Moral K.Suzuki

Talks about:

design (12) synthesi (10) softwar (10) system (9) base (9) embed (8) circuit (6) level (5) asynchron (4) schedul (4)

Person: Luciano Lavagno

DBLP: Lavagno:Luciano

Contributed to:

2013

2012

2011

2009

2007

2005

2004

2003

2002

2001

2000

1999

1998

1997

1996

1995

1992

1991

Wrote 37 papers:

DATE-2013-KondratyevLMW #evaluation #synthesis: Share with care: a quantitative evaluation of sharing approaches in high-level synthesis (AK, LL, MM, YW), pp. 1547–1552.
DATE-2012-KondratyevLMW #synthesis #trade-off: Exploiting area/delay tradeoffs in high-level synthesis (AK, LL, MM, YW), pp. 1024–1029.
SCAM-2012-LazarescuL #analysis #c #dependence #parallel #source code: Dynamic Trace-Based Data Dependency Analysis for Parallelization of C Programs (MTL, LL), pp. 126–131.
DATE-2011-KondratyevLMW #pipes and filters #synthesis: Realistic performance-constrained pipelining in high-level synthesis (AK, LL, MM, YW), pp. 1382–1387.
DAC-2009-TuncerCL #adaptation: Enabling adaptability through elastic clocks (ET, JC, LL), pp. 8–10.
DAC-2007-AndrikosLPS: A Fully-Automated Desynchronization Flow for Synchronous Circuits (NA, LL, DP, CPS), pp. 982–985.
DATE-2005-LavagnoPSW #design #slicing: A Time Slice Based Scheduler Model for System Level Design (LL, CP, VS, YW), pp. 378–383.
DATE-v1-2004-BrunelNFGL #development #named #process: SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract (JYB, MDN, AF, PG, LL), pp. 358–363.
DATE-v2-2004-CortadellaKLLS #approach #automation: From Synchronous to Asynchronous: An Automatic Approach (JC, AK, LL, KL, CPS), pp. 1368–1369.
DATE-v2-2004-RosaPGL #configuration management #framework #implementation: Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform (ALR, CP, FG, LL), pp. 1218–1223.
DATE-2003-RosaLP #configuration management #design #hardware: Hardware/Software Design Space Exploration for a Reconfigurable Processor (ALR, LL, CP), pp. 10570–10575.
DATE-2003-VanzagoBCL #configuration management #design #framework #platform #protocol: Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform (LV, BB, JC, LL), pp. 10662–10667.
DATE-2002-ArrigoniDPLW #scheduling: False Path Elimination in Quasi-Static Scheduling (GA, LD, CP, LL, YW), pp. 964–970.
DAC-2001-ReyneriCSL #co-evolution #design #hardware #library: A Hardware/Software Co-design Flow and IP Library Based of SimulinkTM (LMR, FC, AS, LL), pp. 593–598.
DATE-2001-PasseroneWL #generative #graph #scheduling: Generation of minimal size code for scheduling graphs (CP, YW, LL), pp. 668–673.
DAC-2000-CortadellaKLMMPWS #embedded #generative #scheduling: Task generation and compile-time scheduling for mixed data-control embedded software (JC, AK, LL, MM, SM, CP, YW, ALSV), pp. 489–494.
DAC-2000-HsiehBLS #design #embedded #performance: Efficient methods for embedded system design space exploration (HH, FB, LL, ALSV), pp. 607–612.
DATE-2000-KimLS #embedded #optimisation: Free MDD-Based Software Optimization Techniques for Embedded Systems (CK, LL, ALSV), pp. 14–18.
DATE-2000-LajoloRDL #design #performance: Efficient Power Co-Estimation Techniques for System-on-Chip Design (ML, AR, SD, LL), pp. 27–34.
DATE-2000-LajoloRRVL #co-evolution #dependence #design #framework: Evaluating System Dependability in a Co-Design Framework (ML, MR, MSR, MV, LL), pp. 586–590.
DAC-1999-KondratyevCKLY #automation #optimisation #synthesis: Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems (AK, JC, MK, LL, AY), pp. 110–115.
DAC-1999-LavagnoS #design #named #specification: ECL: A Specification Environment for System-Level Design (LL, ES), pp. 511–516.
DAC-1999-SgroiL #embedded #petri net #synthesis #using: Synthesis of Embedded Software Using Free-Choice Petri Nets (MS, LL), pp. 805–810.
DATE-1999-TabbaraSSFL #modelling #performance #using: Fast Hardware-Software Co-simulation Using VHDL Models (BT, MS, ALSV, EF, LL), p. 309–?.
DAC-1998-CuattoPLJDSS #case study #design #embedded: A Case Study in Embedded System Design: An Engine Control Unit (TC, CP, LL, AJ, AD, CS, ALSV), pp. 804–807.
DAC-1998-HongBLS #embedded: Don’t Care-Based BDD Minimization for Embedded Software (YH, PAB, LL, ES), pp. 506–509.
DAC-1997-CabodiCLQ #approach #clustering #effectiveness #scalability #traversal: Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits (GC, PC, LL, SQ), pp. 728–733.
DAC-1997-PasseroneLCS #analysis #hardware #performance #prototype #trade-off: Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis (CP, LL, MC, ALSV), pp. 389–394.
EDTC-1997-CabodiCLQ #synthesis #verification: Verification and synthesis of counters based on symbolic techniques (GC, PC, LL, SQ), pp. 176–181.
EDTC-1997-CortadellaKKLY #composition #independence: Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis (JC, MK, AK, LL, AY), pp. 98–105.
DAC-1996-BalarinHJLS #embedded #network #verification: Formal Verification of Embedded Systems based on CFSM Networks (FB, HH, AJ, LL, ALSV), pp. 568–571.
DAC-1996-CortadellaKKLY #encoding #synthesis #tool support: Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis (JC, MK, AK, LL, AY), pp. 63–66.
PDP-1996-GregorettiILPR #design #implementation: Design and Implementation of the Control Structure of the PAPRICA-3 Processor (FG, FI, LL, RP, LMR), pp. 290–296.
DAC-1995-ChiodoGJLHSSS #embedded #source code #synthesis: Synthesis of Software Programs for Embedded Control Applications (MC, PG, AJ, LL, HH, KS, ALSV, ES), pp. 587–592.
DAC-1995-LavagnoMSS #design #power management #synthesis: Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool (LL, PCM, AS, ALSV), pp. 254–260.
DAC-1992-LavagnoMBS #graph #problem: Solving the State Assignment Problem for Signal Transition Graphs (LL, CWM, RKB, ALSV), pp. 568–572.
DAC-1991-LavagnoKS #algorithm #synthesis: Algorithms for Synthesis of Hazard-Free Asynchronous Circuits (LL, KK, ALSV), pp. 302–308.