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Travelled to:
2 × USA
Collaborated with:
S.Gu J.Sun Y.Wu S.Venkataraman W.K.Fuchs J.H.Patel
Talks about:
scan (4) test (3) cost (2) architectur (1) partial (1) circuit (1) inform (1) effect (1) design (1) applic (1)

Person: Dong Xiang

DBLP DBLP: Xiang:Dong

Contributed to:

DAC 20032003
DAC 19961996

Wrote 2 papers:

DAC-2003-XiangGSW #architecture #effectiveness #testing
A cost-effective scan architecture for scan testing with non-scan test power and test application cost (DX, SG, JGS, YLW), pp. 744–747.
DAC-1996-XiangVFP #design
Partial Scan Design Based on Circuit State Information (DX, SV, WKF, JHP), pp. 807–812.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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