Travelled to:2 × France
2 × Germany
5 × USA
Collaborated with:T.Lam M.Marek-Sadowska X.Yang C.Cheung Y.Diao X.Wei W.Tang D.I.Cheng C.L.Zhou W.Lo D.Xiang S.Gu J.Sun H.Fan J.Liu
Talks about:circuit (3) test (3) scan (3) techniqu (2) perturb (2) scheme (2) remov (2) logic (2) fpgas (2) coupl (2)
Person: Yu-Liang Wu
DBLP: Wu:Yu=Liang
Contributed to:
20152012
2010200720032001200119951994Wrote 10 papers:
- DATE-2015-DiaoLWW #reduction
- A coupling area reduction technique applying ODC shifting (YD, TKL, XW, YLW), pp. 1461–1466.
- DATE-2015-WeiDLW #metaprogramming
- A universal macro block mapping scheme for arithmetic circuits (XW, YD, TKL, YLW), pp. 1629–1634.
- DATE-2012-YangLTW #modelling
- Almost every wire is removable: A modeling and solution for removing any circuit wire (XY, TKL, WCT, YLW), pp. 1573–1578.
- DAC-2010-YangLW #complexity #fault #named
- ECR: a low complexity generalized error cancellation rewiring scheme (XY, TKL, YLW), pp. 511–516.
- DAC-2007-ZhouTLW #how #logic
- How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs (CLZ, WCT, WHL, YLW), pp. 922–927.
- DAC-2003-XiangGSW #architecture #effectiveness #testing
- A cost-effective scan architecture for scan testing with non-scan test power and test application cost (DX, SG, JGS, YLW), pp. 744–747.
- DAC-2001-FanLWC #2d #design #on the
- On Optimum Switch Box Designs for 2-D FPGAs (HF, JL, YLW, CCC), pp. 203–208.
- DATE-2001-CheungWC #clustering #logic #using
- Further improve circuit partitioning using GBAW logic perturbation techniques (CCC, YLW, DIC), pp. 233–239.
- DAC-1995-WuM #2d #approach #optimisation #orthogonal
- Orthogonal Greedy Coupling — A New Optimization Approach to 2-D FPGA Routing (YLW, MMS), pp. 568–573.
- EDAC-1994-WuM #2d #array #performance #programmable
- An Efficient Router for 2-D Field Programmable Gate Arrays (YLW, MMS), pp. 412–416.