Travelled to:2 × Germany
4 × France
Collaborated with:M.Renovell Y.Bertrand S.Bernard A.A.Rekik N.Dumas F.Mailly P.Nouet H.Ayari M.Comte V.Kerzerho É.F.Cota L.Carro M.Lubaszewski
Talks about:analog (4) implement (3) test (2) bist (2) acceleromet (1) histogram (1) capacitor (1) techniqu (1) configur (1) respons (1)
Person: Florence Azaïs
DBLP: Aza=iuml=s:Florence
Contributed to:
201420112001200019981997Wrote 6 papers:
- DATE-2014-AyariABCKR #predict
- New implementions of predictive alternate analog/RF test with augmented model redundancy (HA, FA, SB, MC, VK, MR), pp. 1–4.
- DATE-2011-RekikADMN #development #evaluation
- An electrical test method for MEMS convective accelerometers: Development and evaluation (AAR, FA, ND, FM, PN), pp. 806–811.
- DATE-2001-AzaisBBR #implementation #linear
- Implementation of a linear histogram BIST for ADCs (FA, SB, YB, MR), pp. 590–595.
- DATE-2000-CotaRABCL #reuse
- Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte (ÉFC, MR, FA, YB, LC, ML), pp. 226–230.
- DATE-1998-RenovellAB #implementation #multi
- Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits (MR, FA, YB), pp. 815–821.
- EDTC-1997-RenovellAB
- On-chip analog output response compaction (MR, FA, YB), pp. 568–572.