Travelled to:3 × Germany
4 × France
Collaborated with:F.Azaïs Y.Bertrand J.Figueras J.M.Portal Y.Zorian S.Bernard E.I.Vatajelu R.Rodríguez-Montañés M.Indaco P.Prinetto H.Ayari M.Comte V.Kerzerho É.F.Cota L.Carro M.Lubaszewski C.Metra G.A.Mojoli S.Pastore D.Salvi G.R.Sechi
Talks about:analog (4) test (4) implement (3) configur (3) techniqu (2) logic (2) fpga (2) bist (2) base (2) interconnect (1)
Person: Michel Renovell
DBLP: Renovell:Michel
Contributed to:
2015201420012000199919981997Wrote 9 papers:
- DATE-2015-VatajeluRIRPF #estimation #metric #robust
- Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell (EIV, RRM, MI, MR, PP, JF), pp. 447–452.
- DATE-2014-AyariABCKR #predict
- New implementions of predictive alternate analog/RF test with augmented model redundancy (HA, FA, SB, MC, VK, MR), pp. 1–4.
- DATE-2001-AzaisBBR #implementation #linear
- Implementation of a linear histogram BIST for ADCs (FA, SB, YB, MR), pp. 590–595.
- DATE-2000-CotaRABCL #reuse
- Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte (ÉFC, MR, FA, YB, LC, ML), pp. 226–230.
- DATE-1999-RenovellPFZ #configuration management #interface #logic #testing
- Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s (MR, JMP, JF, YZ), pp. 618–622.
- DATE-1998-MetraRMPPFZSS #novel #testing
- Novel Technique for Testing FPGAs (CM, MR, GAM, JMP, SP, JF, YZ, DS, GRS), pp. 89–94.
- DATE-1998-RenovellAB #implementation #multi
- Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits (MR, FA, YB), pp. 815–821.
- DATE-1998-RenovellPFZ #approach #configuration management #logic
- RAM-Based FPGA’s: A Test Approach for the Configurable Logic (MR, JMP, JF, YZ), pp. 82–88.
- EDTC-1997-RenovellAB
- On-chip analog output response compaction (MR, FA, YB), pp. 568–572.